Friday, May 18, 2012     Register | Login | Search | Contact Us
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Subject: Gate-leve sim, sdf back annotation warnings
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
raajaavishnu
Posts: 1
Online: User is Offline
11/14/2007 8:47 PM  
I am running sdf-back-annotated Gate-level sims. During ncelab, I see the following warnings: 1. ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH CP Q) of instance :DUT0.u_core.u_cfg.u1_xxxx_apb.bus_sync1.clk_gate_dest_bus_reg.latch of module c065std_cell_icgX10 <../TIMING/xxxx_netlist.sdf, line 329587>. The corresponding line (line 329587) in the SDF file is

DELAY
    (ABSOLUTE
    (IOPATH CP Q (0.173::0.456) (0.183::0.486))
    )
  )
When I check the verilog for the standard cell library for the cell in question I see the following:

 specify

    (CP => Q) = (`c065std_cell_icgX10_CP_F_Q_F, `c065std_cell_icgX10_CP_R_Q_R);
    $setuphold(posedge CP, posedge TE, `c065std_cell_icgX10_TE_CP_SETUP, `c065std_cell_icgX10_TE_CP_HOLD, Notifier, ,EX ,CPdly, TEdly);
    $setuphold(posedge CP, negedge TE, `c065std_cell_icgX10_TE_CP_SETUP, `c065std_cell_icgX10_TE_CP_HOLD, Notifier, ,EX ,CPdly, TEdly);
    $setuphold(posedge CP, posedge E, `c065std_cell_icgX10_E_CP_SETUP, `c065std_cell_icgX10_E_CP_HOLD, Notifier, ,TEX ,CPdly, Edly);
    $setuphold(posedge CP, negedge E, `c065std_cell_icgX10_E_CP_SETUP, `c065std_cell_icgX10_E_CP_HOLD, Notifier, ,TEX ,CPdly, Edly);
    $width(negedge CP, `c065std_cell_icgX10_CP_PWL, 0, Notifier);

 endspecify
Looking at this there does seem to be a path from CP -> Q. Can someone tell me why I still see this warning? 2. For the same module as above, I see the following warning ncelab: *W,SDFNSB: Attempt to annotate specify block data of instance :DUT0.u_core.u_cfg.u1_xxxx_apb.bus_sync1.clk_gate_dest_bus_reg.latch of module c065std_cell_icgX10, which has no specify block <../TIMING/xxxx_netlist.sdf, line 329591>. The corresponding section in the SDF file (line 329591) is:

(TIMINGCHECK
    (WIDTH (negedge CP) (0.120::0.120))
    (SETUP (posedge TE) (posedge CP) (0.162::0.162))
    (SETUP (negedge TE) (posedge CP) (0.084::0.084))
    (SETUP (posedge E) (posedge CP) (0.295::0.295))
    (SETUP (negedge E) (posedge CP) (0.246::0.246))
    (HOLD (posedge TE) (posedge CP) (-0.115::-0.115))
    (HOLD (negedge TE) (posedge CP) (-0.071::-0.071))
    (HOLD (posedge E) (posedge CP) (-0.128::-0.128))
    (HOLD (negedge E) (posedge CP) (-0.082::-0.082))
  )
Looking at the afore-mentioned "specify" block can anyone help me understand the reason for this second warning? 3. Also the specify block contains $setuphold in an extended format. Can someone please explain the four fields after "notifier"? Thanks in advance Vishnu
synthman
Posts: 17
Online: User is Offline
11/15/2007 8:57 AM  
Not sure what's the problem with the CP->Q arc, what are the specparams for:
`c065std_cell_icgX10_CP_F_Q_F, `c065std_cell_icgX10_CP_R_Q_R

In problem #2, ncsim expects a combined setuphold check arc. RC only writes them separately, there's no option to merge setuphold check in the current 7.1 version. You might want to try the workaround using write_sdf in bgx_shell (in the same RC installation).
tmackett
Posts: 34
Online: User is Offline
3/12/2008 7:20 PM  
I can't speak for RC's switches and features, but I can shed some light on SDF annotation from a simulation point of view.  There is always great confusion over this.  Also note that you can have negative values with SETUPHOLD (and RECREM), but you can only have positive values for SETUP and HOLD.  NCSim does a nice job of simulating the negative timing checks (it's just a time reference).  Sometime you'll see something like "timing yada yada from here to there cancelled" in the simulation log, this is OK, it's just a warning to tell you that a different path fullfilled the timing.  Below are some notes on SDF annotation for simulation.

SDF file can be more general than Verilog

For instance if SDF has:

(HOLD (posedge resetb) (posedge phi) (-0.003:-0.003:-0.003))

and the Verilog has:

$hold(posedge phi &&& enableRRV, posedge resetb, 0, notify_reg);

the SDF is giving a general case, that posedge phi can annotate to a posedge phi + some condition.

The other case, Verilog being more general cant work because there would be confusion of exactly what timing to implement.

If SDF says annotate BLUE and the Verilog has a LIGHT BLUE flavor, then it will annotate.

If Verilog says LIGHT BLUE, then the SDF must have a LIGHT BLUE to annotate


Todd Mackett
Cadence Incisive
Posting to forums is available to community members only.
Login or Register

Forums > Digital IC > Synthesis and test > Gate-leve sim, sdf back annotation warnings


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.