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Subject: Mismatch between RTL and synthesis result (CDFG-511)
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weidi1
Posts: 0
Online: User is Offline
12/06/2004 3:41 AM  
I experience a mismatch between behavior of RTL and the Ambit Synthesis Result; whereby Ambit displays the following WARNING:
--> WARNING: Possibly an 'X' or 'Z' value propagated to a control statement
that may cause simulation mismatches between the original and
synthesized designs (File ../RTL/com.v, Line 3957) .
What is CDFG-511?
Details:
The design is an FSM which has outputs dependent from the next_state, i.e. mealy outputs. In the synthesis result the next_state after the power on reset evaluates to 'x' although the next_state is in this case only dependent from the current state which is well defined by the reset. Ambit involves additional signals in the calculation of the next_state, which are not defined at this time. Ambit Version is v5.7-s133.
synthman
Posts: 17
Online: User is Offline
12/06/2004 7:28 AM  
Hello weidi1,
We suggest you use the latest 5.14 version. The 5.7 version is about 2 yrs old. You might have some undriven signals propagated to the control logic. Check the settings of the variable hdl_undriven_net/port/pin_value and set it to the expected value in your design.

CDFG (Control Data Flow Graph) indicates this warning occurs during the build_generic process where BG builds the generic data base from your RTL.
weidi1
Posts: 0
Online: User is Offline
12/09/2004 5:21 AM  
Hello synthman,

Thanks for the hints.
I tried 5.14 but the warning is the same as is the erroneos behavior of the synthesized circuit. The strange thing is, it works if I force Ambit to synthesize the output logic dependent on the next_state (and the current state) into a separate module; no warning, correct behavior.
What do You exactly mean by ""undriven signals propagated to the control logic""?
synthman
Posts: 17
Online: User is Offline
12/09/2004 7:19 AM  
Hi weidi1,
I meant there might be some undriven signal propagated to the control statement like 'case', 'if'. Do you see any undriven net reported from 'check_netlist'?

Seems like this is something specific to your design that triggers the warning. I don't think we can resolve it here in this forum. If you can send that piece of RTL to Cadence Support, we can investigate further.
crispy_duck
Posts: 0
Online: User is Offline
2/06/2006 7:01 AM  
weidi1,

Might be a stupid question, but is the problem occuring where you have a "case" statement in the code for defining which state is "next_state"?

If so, does this case statement have an "others" clause covering all possibilities not explicitly in the rest of the statement?

Might be worth checking.

CD
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Forums > Digital IC > Synthesis and test > Mismatch between RTL and synthesis result (CDFG-511)


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