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Subject: memory synthesis RTL Compiler commands
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alexsieh
Posts: 7
Online: User is Offline
12/13/2007 1:39 PM  
I am trying to synthesize my RTL code which instantiates a memory.
I have the memory SIMULATION models which are not synthesizable.
I also have its *.v, *.lib, *.lef, *.tlf files.

question: How do I synthesize my RTL code using the memory model files? Do I let it turn into a blackbox during synthesis?

Someone else wrote to me:
To integrate the block, the *.lib file can be read into Synopsys (read_lib command) and transformed to a compiled Synopsys library (write_lib command) to get to a *.db file. This *.db file needs to be in the link_library variable (together with all other libraries needed to get the circuit together) and everything should work fine then. In the code of the circuit, the memory is called like any other cell then.

For RTL Compilier, there should be similar commands like read_lib/write_lib to get from the *.lib to the compiled library that the synthesizer tool needs.

I know Synopsys DC Compiler "read_lib" is equivalent to "set_attribute library".
Is there an equivalent RC command to "write_lib" ?

Thank you for your kind help,
aps
grasshopper
Posts: 48
Online: User is Offline
12/13/2007 1:45 PM  
Hi aps,

sounds like you already have the .lib for your memory so you should be ok if you specify the .lib in your library attribute and then you will no longer need to read the behavioral RTL

good luck,
gh-
sporadic crash
Posts: 43
Online: User is Offline
12/14/2007 4:22 AM  
Hi Alex,

ASIC synthesizers do no infer memories from RTL in the way FPGA synthesis tools do. Wafer fabs do not give parametric timing data so that an ASIC synthesis tool recognizes the size of the RAM and infers the RAM core automatically.

Therefore you must use a special program called memory generator or macro generator, which generates memories out of synthesis. Then you can add it as *.lib file which is actually timing data, not RTL. This program is given usually by wafer fab.

To your 2nd question:
RTL Compiler does not support Synopsys file formats and convert libraries between various formats. And also, you don't need to convert libraries. *.lib (liberty) file format is a standard file format (like IBIS specification) among all EDA tools.

HTH.
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Forums > Digital IC > Synthesis and test > memory synthesis RTL Compiler commands


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