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Subject: Can't time design correctly with generated clock
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mximdal
Posts: 0
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2/10/2005 9:03 AM  
When the source clock for a generated clock is from an internal module, report_timing times launch and capture off of the same edge of this generated clock.

create_clock -name sclk -period 10 top/U1/U23/port2
create_generated_clock -name gclk -source sclk -divide_by 8
....

When doing timing report, the launch clock is gclk at time 0 and capture clock is gclk at time 0. So, the path always misses timing.

Have anybody seen this in their design?
synthman
Posts: 17
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2/10/2005 9:13 AM  
Do you mean report_timing in late mode or early mode? In early mode, launch and capture edge are both at 0.
synthman
Posts: 17
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2/10/2005 9:19 AM  
Another thing to check is to use 'report_clocks -generated' to see if the phase shifts for this clock are correct.
mximdal
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2/11/2005 3:56 PM  
Synthman,

Thanks for the reply. Figured out that the clock should be coming from top port. So things are fine now. ;-)
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Forums > Digital IC > Synthesis and test > Can't time design correctly with generated clock


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