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Subject: RTL Compiler Help .. Urgent !!!!!
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kevinthomasp
Posts: 2
Online: User is Offline
4/17/2008 9:46 PM  
We are having licence only for RTL compiler not for Ultra. We tried inserting buffer using path_delay command in RTL compiler, but not working. It is not inserting buffer in verilog file generated eventhough it is mentioning in the timing report. Is it possible to insert buffer according to our constraints using any command in RTL compiler?

Kevin
grasshopper
Posts: 48
Online: User is Offline
4/18/2008 8:23 AM  
Hi Kevin,

not sure what you are trying to do but if you are trying to use path_delay to insert buffers for min_delay type things, RC does not perform any min_del analysis as far as I know. Hold fixing and min_del type analysis is much better addressed in placement tools where the wire numbers are 100% accurate. You can certainly use edit_netlist or insert_io_buffer in RC to insert buffers but if you know exactly what you want, why don't you just hand-instantiate ?

gh-
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Forums > Digital IC > Synthesis and test > RTL Compiler Help .. Urgent !!!!!


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