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Naderi
Posts: 24
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| 5/16/2008 8:39 AM |
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| Hello All,
I am running into problem with machine memory and tool break for synthesizing a 4M-gate verilog code.
Is Cadence-BuildGates able to synthesis codes in hierarchy levels?
My feeling is if BuildGates can optimize only the lowest level of the design blocks, and then only by using them in the higher levels, less effort and memory should be required than synthesizing the whole design in one shut.
Thanks,
Ali
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