I have the following interfaces for two submodules
module comparator7(a, b, clk, ce, reset, qa_gt_b);
input clk; // <== clock signal
input reset; // <== reset signal
input ce; // <== chip enable signal
input Δ:0]a; // <== first input to compare
input Δ:0]b; // <== second input to compare
output reg qa_gt_b; // <== output signal
// some other logic
endmodule
module em(clk, reset, in_bit, update, address, out_bit);
input clk; // <== clock signal
input reset; // <== reset signal
input in_bit; //
input update; //
input Γ:0] address; //
output out_bit;
wire mux_out;
reg out_bit;
reg ⏋:0] edge_mem;
// some other logic
endmodule
The two are only sub modules in the design and there are instanciated and connected in an upper layer module as follows
module eq_node_deq_5(clk, reset, decoding_enable, p_ch, load_prob_enable, prob_id, node_id, load_shift_enable,in0, in1, in2, in3, in4, address0_0, address0_1, address0_2, address0_3, address0_4, address0_5, address1_0, address1_1, address1_2, address1_3, address1_4, address1_5, address2_0, address2_1, address2_2, address2_3, address2_4, address2_5, address3_0, address3_1, address3_2, address3_3, address3_4, address3_5, address4_0, address4_1, address4_2, address4_3, address4_4, address4_5, out0, out1, out2, out3, out4, out_ch ); //==> goes to UD counter
input clk; // <== clock signal
input reset; // <== reset signal
input decoding_enable; // <== from the CU
input Δ:0] p_ch; // <== from the CU
input load_prob_enable; // <== from the CU
input Γ:0] prob_id; // <== from the CU
input Γ:0] node_id; // <== from the CU
input load_shift_enable;// <== from the CU
input in0; // <== comes from ch node
input in1; // <== comes from ch node
input in2; // <== comes from ch node
input in3; // <== comes from ch node
input in4; // <== comes from ch node
input address0_0; // <== comes from Random Engine
input address0_1; // <== comes from Random Engine
input address0_2; // <== comes from Random Engine
input address0_3; // <== comes from Random Engine
input address0_4; // <== comes from Random Engine
input address0_5; // <== comes from Random Engine
input address1_0; // <== comes from Random Engine
input address1_1; // <== comes from Random Engine
input address1_2; // <== comes from Random Engine
input address1_3; // <== comes from Random Engine
input address1_4; // <== comes from Random Engine
input address1_5; // <== comes from Random Engine
input address2_0; // <== comes from Random Engine
input address2_1; // <== comes from Random Engine
input address2_2; // <== comes from Random Engine
input address2_3; // <== comes from Random Engine
input address2_4; // <== comes from Random Engine
input address2_5; // <== comes from Random Engine
input address3_0; // <== comes from Random Engine
input address3_1; // <== comes from Random Engine
input address3_2; // <== comes from Random Engine
input address3_3; // <== comes from Random Engine
input address3_4; // <== comes from Random Engine
input address3_5; // <== comes from Random Engine
input address4_0; // <== comes from Random Engine
input address4_1; // <== comes from Random Engine
input address4_2; // <== comes from Random Engine
input address4_3; // <== comes from Random Engine
input address4_4; // <== comes from Random Engine
input address4_5; // <== comes from Random Engine
output out0; // ==> goes to chk node
output out1; // ==> goes to chk node
output out2; // ==> goes to chk node
output out3; // ==> goes to chk node
output out4; // ==> goes to chk node
output out_ch;
wire em0_sig_in;
wire em1_sig_in;
wire em2_sig_in;
wire em3_sig_in;
wire em4_sig_in;
wire em0_sig_out;
wire em1_sig_out;
wire em2_sig_out;
wire em3_sig_out;
wire em4_sig_out;
wire update0;
wire update1;
wire update2;
wire update3;
wire update4;
wire j0;
wire j1;
wire j2;
wire j3;
wire j4;
wire k0;
wire k1;
wire k2;
wire k3;
wire k4;
wire in_ch;
wire j_ch;
wire k_ch;
wire out0;
wire out1;
wire out2;
wire out3;
wire out4;
wire out_ch;
wire cmp_en;
reg sig_ch;
assign cmp_en = (prob_id == node_id & load_prob_enable)? 1'b1 : 1'b0 ;
//TODO: validate the first two address lines connection with SAEED
comparator7 comparator(.a(p_ch), .b({address4_0, address3_5, address3_4, address3_3, address3_2, address3_1, address3_0}), .clk(clk), .ce(cmp_en), .reset(reset), .qa_gt_b(in_ch));
em em0(.clk(clk), .reset(reset), .in_bit(em0_sig_in), .update(update0), .address({address0_5, address0_4, address0_3, address0_2, address0_1, address0_0}), .out_bit(em0_sig_out));
// some other glue logic
endmodule
When synthesizing the design with BuildGates, I get the following warning message. I cannot understand why I get this warning since all the address*_* signals are driven only by input of the top layer. In all other submodules these signals are all input signals and not output. The same holds for the clk and the reset signal
--> WARNING: Potential multiply-driven net 'address4_5' found in module 'eq_node_deq_5' <FNP-537>.
--> WARNING: Potential multiply-driven net 'address3_5' found in module 'eq_node_deq_5' <FNP-537>.
--> WARNING: Potential multiply-driven net 'address3_4' found in module 'eq_node_deq_5' <FNP-537>.
--> WARNING: Potential multiply-driven net 'address3_3' found in module 'eq_node_deq_5' <FNP-537>.
--> WARNING: Potential multiply-driven net 'address3_2' found in module 'eq_node_deq_5' <FNP-537>.
--> WARNING: Potential multiply-driven net 'address3_1' found in module 'eq_node_deq_5' <FNP-537>.
--> WARNING: Potential multiply-driven net 'address3_0' found in module 'eq_node_deq_5' <FNP-537>.
--> WARNING: Potential multiply-driven net 'reset' found in module 'eq_node_deq_5' <FNP-537>.
--> WARNING: Potential multiply-driven net 'clk' found in module 'eq_node_deq_5' <FNP-537>.
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