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Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

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Subject: CDNLive Silicon Valley 2006
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DaveG
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Posts: 4
Online: User is Offline
8/17/2006 12:31 PM  
Hello!

With CDNLive! Silicon Valley coming up, I'd like to take this opportunity to encourage folks to come and take advantage of this event.
The CDNLive! 2006 Silicon Valley Conference Schedule is now online at:
    http://www.cadence.com/cdnlive/na/schedule2006_tues.aspx

I wasn't able to attend CNDLive! last year, but I had attended the Cadence Users Group meetings in the past and found the presenters to be knowlegdeable and ultimately willing to share their learnings.  The papers were valuable as was the opportunity to meet and network with Cadence developers. 

As a hardware designer and EDA tool user, it was always good to hear others' experiences, methodologies and tools hints.  I'm looking forward to this year's CDNLive! event and hope to meeting you there!

A couple of papers that I'm interested in seeing and might be of interest to forum members are:

Session 2.4.1 on Tuesday 3:30pm-4:15pm
 "Best known methods for using Cadence Conformal LEC at Intel",
  by Erik Seligman, Intel

Session Session 2.7 on Wednesday 11:10am-11:55am
 "Formal and Structural Analysis of Power Management Designs Using Conformal Low Power",
  by Lam Ho, Texas Instruments

You can register for the Silicon Valley event at the CDNLive! website:
    http://www.cadence.com/cdnlive

---Dave

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Forums > Digital IC > Formal verification > CDNLive Silicon Valley 2006


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