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Forums > Digital IC > Formal verification

Subject: How FEV saved our STA
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evenditti
Moderator
Posts: 23
Online: User is Offline
8/21/2006 9:06 PM  
Hello Everybody,

I thought I would shared a recent experiece I had which will show you another side of FEV.

During my last project we kept running in paths not being properly disable during test mode (clock mux not propagating the right clock or propagating multiple clocks, clock gating not being turned off, bypass inactive) and some similar issues.

Now we are in 65nm and using a custom library so we thought we had some modeling issues and spent a long time reviewing cells modeling without finding anything explaining the issues we were having.

After discussing with the engineer in charge of our top level FEV, he mentioned that we were clean and only had a few inverted equivalent which he verified and were fine. Here I asked him to provide me the list so I can try to understand why the synthesis too was doing that when I was not expecting it (turn out it was an option in DC ). Also while reviewing the list I noticed that a few of the FF in our test controller were inverted equivalent and BINGO!!! Here goes the problem.

Sure enough after the STA engineer, inverted the case_analysis our STA started to make sense.

Here is what we learned out of this:

  - Have better documentation (bit hallway discussion and email exchange any day)
  - Keep current with FEV status and inverted equivalent FF to check that important FF in your design are not impacted.

The weirdest thing during the whole time was that the ATPG gate level sims keep passing and we could not explain why....

I hope this will help somebody else and if not that you enjoyed the story.

Thanks,
Eric.
Eric Venditti
EngHan
Posts: 65
Online: User is Offline
8/22/2006 2:58 AM  
Hi Eric and all,

I have a related question here.

Some FFs are status FF, like test-modes etc. Sometime we have to put a set-case-analysis on the output of those FFs. However, after synthesis, sometime the Q-Bar output is used, and thus the SDC is broken. Is there a way to ask the synthesis tool not to do this (i.e. use Q, and not Q-Bar) for some selected reg?

Regards,
Eng Han
evenditti
Moderator
Posts: 23
Online: User is Offline
11/01/2006 10:36 PM  
Hi Eng,

sorry for not responding earlier but I missed your post.

I believe there is a way to specify which FFs a given register can mapped to but often in practice this is very hard to manage and most likely synthesis tool dependant. If you tell me which tool you are using I can try to find out.

Best solution is to instantiate the FF you want directly in your RTL (using a intermediate level of hierarchy so you can have either the gate or some rtl for simulation and other analysis purposes) and to put a size_only or dont_touch attribute on those FFs.

Regards,
Eric.
Eric Venditti
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Forums > Digital IC > Formal verification > How FEV saved our STA


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