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Forums > Digital IC > Formal verification

Subject: Reading Netlists with SEQGEN primitive
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jbusco@nvidia.com
Posts: 2
Online: User is Offline
9/18/2006 9:20 AM  
I wonder if others have solutions for reading netlists containing "SEQGEN" generic registers into LEC? If I read an RTL design into "another synthesis tool" and write out the netlist before technology mapping, the registers are implemented with these generic flip-flops. Any tricks to deal with this? Is there a SEQGEN Verilog model available, for example? I know I could run mapping in the synthesis tool, but then you're not strictly verifying the pre-mapping netlist.
croy
Posts: 54
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9/25/2006 7:46 AM  
Hi

I don't see SEQGEN defined in gtech.v. It's probably relatively easy to define that cell though, if you know the ports and the behaviour.

Why do you want to read that netlist in though?

Cheers,
Chrystian
jbusco@nvidia.com
Posts: 2
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9/26/2006 9:48 AM  
I could hunt down the spec for SEQGEN and model it myself. Was hoping someone had done it before. :-) I want to read this pre-techonology-mapping netlist because Conformal is having trouble to verify RTL vs. the final netlist, and I want to try to make it easier by verifying the first netlist I can dump out of the synthesis tool. Regards, John
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Forums > Digital IC > Formal verification > Reading Netlists with SEQGEN primitive


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