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Subject: TIP OF THE MONTH: Recommended modeling directives for RTL-gate
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croy
Posts: 54
Online: User is Offline
12/07/2006 5:50 AM  
Here's what I use as a starting point for all RTL-gate runs:

  set flatten model -gated_clock
  set flatten model -seq_constant
  set flatten model -seq_constant_x_to 0

as synthesis will often do all these transformations. It's also recommended to run:

  remodel -seq_constant -seq_constant_feedback -repeat
  map key points

after 'set system mode lec', if anything is not-mapped at that point.

I also find it useful to set these:

  set flatten model -nodff_to_dlat_feedback
  set flatten model -nodff_to_dlat_zero

as I have yet to see an implementation tool actually do these changes. Changing the default here should prevent latches from showing up in the compare report.
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Forums > Digital IC > Formal verification > TIP OF THE MONTH: Recommended modeling directives for RTL-gate


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