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anssprasad
Posts: 19
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3/01/2007 3:37 AM
Hi I have tried using "add net constraints" command to place one-cold constraints on a tristate enable bus. In the command line we need to specify the "net pathname" on which the constraints are to be enforced. The bus here is 20-bit. How should the net pathname be specified to make this 20-bit bus signals one_hot or one_cold. The bus was declared as follows: ten_bus ⎟:0] The command I used was add net constraints one_hot /ren_bus⎟] What would the above command mean? Should we not specify all the nets' pathnames on the bus? Is it sufficient to specify the pathname of one net on the bus? I could not get much info regarding the functionality of this command. I would be obliged if anyone can throw some light. Thanks Prasad.

bryan
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3/01/2007 2:22 PM
Depending on the mode vpx or tcl you are probably pattern matching for 1 or 9. Try executing the command in vpx mode and escape the [] with \ and use a * if you want all the bits to be constrainted. or just specifiy the bits your are interested in.

Regards, Bryan

anssprasad
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3/06/2007 12:55 AM
Hi Bryan, I am not sure why my post is looking like that, may be there is a typo error. The command I actually used was add net constraints one_hot /ten_bus⎟] add net constraints one_hot /ten_bus⎟] /ten_bus⎞] ... My intention is to constrain the whole 20 bit bus (i.e, ten_bus⎟] . . . . . . ten_busΎ]) are to be constrained as one_hot. Only the above commands does not fire any error messages and I dont understand how it works. I am afraid I did not uderstand the two modes tcl and vpx you have mentioned. I did not find any such in Conformal EC. Based on your suggestions I have tried using the following command but encountered an error message saying such a net is not found. add net constraints one_hot /ten_bus\[*\] Hope I make some sense. Thanks Prasad

makkarm
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3/07/2007 2:40 AM
Hmm . . Interesting. Designing with tri-states busses is not very common these days. The cap-loads on these (unbuffer'able) wires usually tend to have detrimental ramp times. I have seen people just code it up with muxes and let the synthesis tools do the job. Much easier to verify, time and maintain in general. Anyways, not getting into the philosophy of tri-state busses vs. muxes, here's a answer for the tool. You don't need the preceeding forward slash . . if at the top level . . SETUP> add net constraint one_hot ten_bus⎟] ten_bus⎞] ten_bus⎝] . . . If hiearchical SETUP> add net constraint one_hot mod1/busΑ] mod1/busΐ] . . Once you added your constraints, also do a SETUP> report net constraint to make sure that the constraint has been added. regards, Masood PS: You realize, by adding the one_hot constraint you are just telling Conformal-LEC to ignore the non-one-hot conditions. I am curious, how are you verifying that that this bus really is going to behave as a one-hot and that there would'nt be any contention between the tri-state nets? Is it Simulation?

makkarm
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3/07/2007 2:45 AM
-- Resending reply with hopefully fixing formatting problem -- Designing with tri-states busses is not very common these days. The cap-loads on these (unbuffer'able) wires usually tend to have detrimental ramp times. I have seen people just code it up with muxes and let the synthesis tools do the job. Much easier to verify, time and maintain in general. Anyways, not getting into the philosophy of tri-state busses vs. muxes, here's a answer for the tool. You don't need the preceeding forward slash. If at the top level SETUP> add net constraint one_hot ten_busΐ] ten_busΏ] ten_busΎ] If hiearchical SETUP> add net constraint one_hot mod1/busΑ] mod1/busΐ] Once you added your constraints, also do a SETUP> report net constraint to make sure that the constraint has been added. regards, Masood PS: You realize, by adding the one_hot constraint you are just telling Conformal-LEC to ignore the non-one-hot conditions. I am curious, how are you verifying that that this bus really is going to behave as a one-hot and that there would'nt be any contention between the tri-state nets? Is it Simulation?

anssprasad
Posts: 19
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3/07/2007 3:27 AM
Hi Bryan, I have come to know about the tcl and vpx modes and also discovered that I was running the command in vpx mode only. Thanks Prasad.

anssprasad
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3/07/2007 4:32 AM
Hi Masood, I have used the following command: add net constraints one_hot U9/ZN[nineteen] -both What would the above command mean? After adding this command to the conformal script I found that the tool reports equivalece of the two designs under consideration. I think I should mention all the 20 net_pathnames for the tool to constrain all the bits of the bus as one_hot. Albeit, it looks like the above command has the same functionality. I wanted to know if I am correct in taking such a conclusion. I can put an assertion in the code to ensure that the bus is one_hot, though I am not simulating as of now. Thanks Prasad. P.S: I have used words instead of numerals hoping to overcome some formatting problem while I am posting in this forum. The numerals are being replaced with weird special characters.

makkarm
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3/07/2007 9:14 AM
Hi Prasad, Add the net contraint only one side of the design, -revised preferably And as said do all in one line . . SETUP> add net constaint one_hot ZN[zero] ZN[one] ZN[two] . . . -revised Constraints are essentially assumptions that the Equivalence Checker can use to "ignore" Non-equivalences. For eg. if you apply a one-hot on revised Golden: net1, net2, net3 Revised: net1, net2, net3 Then only conditions where revised is 001, 010, 100 will be honored. A condition such as (G)110 and (R)011 will be ignored even if it is non-equivalent because of the constraint. -- Masood PS: You better simulate the one_hot in a simulator. Also if you have conformal - ASIC license, you may be able to actually verify that your one-hot bus is truly a one-hot formally without vectors. You can invoke that tool by unix> lec -verify From there it is pretty intuitive with a check called bus contention. PPS: There are experts in the support channel who can guide you with this. You may want to file an SR.

anssprasad
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3/08/2007 6:49 AM
Hi Masood, May i know the reason for your preference of constraining the revised alone or only on one side. Thanks for your valuable inputs. I am trying out with the lec -verify feature. Prasad.

bryan
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3/11/2007 9:12 AM
I believe in VPX mode you don't need to escape the [ with the \ command. The wildcarding should work. That siad I have filed several issues over many years trying to get wildcarding to work. You have have to leave off the brackets and put the wildcard at the end of the signal name. Yes I know this might possible match too much and is the basis of the issues I have filed over the years. I am not as up on VPX mode anymore as I use TCL mode exclusively.

Regards, Bryan

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Forums > Digital IC > Formal verification > Using "add net constraints" command in Conformal