Thursday, November 20, 2008     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Digital IC > Formal verification

Subject: Problem with un-mapped elements
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
maurizios
Posts: 8
Online: User is Offline
8/29/2007 1:50 AM  
Hi,
I am trying to run Conformal on RTL vs gate-level netlist. I have noticed that synthesis removed a FF in netlist due to that fact that its D input has been tied to 0. Howver while flattening the netlist the FF is not removed and is reported as unmapped element. As a result some comapre points fail due to the fact that this FF is in the logic cone.
By looking at schematic of golden netlist and tracing back the D input of the FF it looks like this pin is connected to other elementes named DC which shows as connection due to constraint. How can I identify which is the offendign constraitn that originated the problem. report_pin_constraint and report_dynamic_constraint command do no report any constraint.

Thanks
Maurizio Spadari  
Principal Design Engineer
NemeriX SA
croy
Posts: 54
Online: User is Offline
8/29/2007 6:23 AM  
Hi Maurizio

Are you using the following flow?

set flatten model -seq_constant
set flatten model -seq_constant_x_to 0
set flatten model -gated_clock

set system mode lec

remodel -seq_constant -seq_constant_feedback -repeat
map key points

That should take care of removing the constant flop.

A couple more notes:

1) the runtime of the 'remodel' command was dramatically improved in 7.1 compared to 6.2 or earlier versions

2) I have run into a couple cases lately where DC leaves a constant flop in the netlist but optimizes the fanout from that flop based on the constant value (that makes no sense to me but it's functionally correct). The solution is to use "set flatten model -nobalanced_modeling" or to add -nomap to 'set system mode lec' if the number of flops in the design is reasonable (under 50K or so).

Chrystian
maurizios
Posts: 8
Online: User is Offline
8/29/2007 9:33 AM  
Hi Chrystian,
thanks your suggestion worked. Unfortunately now I hit with another problem related to clock gating. I will list it in a separate post.
Maurizio
bryan
Posts: 25
Online: User is Offline
8/29/2007 6:54 PM  
Becareful using sequential propagation. Unless it has been fixed it doesn't always behave as youwould expect. The end result is too much propagation that could mask real bolean non-equilancies. Becareful if you have tied clocks and constant signals like you might have in your test logic.

Given the issues my philosophy has been to not allow sequential optimization in synthesis and thus I won't need in when doing boolean equivalency checking.
Regards,
Bryan
Posting to forums is available to community members only.
Login or Register
Forums > Digital IC > Formal verification > Problem with un-mapped elements


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.