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Forums > Digital IC > Formal verification

Subject: Issue with gated clock
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maurizios
Posts: 8
Online: User is Offline
8/29/2007 9:39 AM  
Hi,
I am doing a c omparison of RTL vs. gate. The original RTL has some clock gating that has been instantiated using technology library gate elements. During sytnhesis further clock gatignf has been added by synthesis tool.
Consequently I have used "set flatten model -gated_clock' to be able to process gated clock elements.
Unfortunately some points miscompated due to the fact that in golden (RTL) design the gated clock appears in the fanin cone of the FF while in the revised does not.
Did I make some wrong switches ?

Thanks
Maurizio
croy
Posts: 54
Online: User is Offline
8/29/2007 1:10 PM  
Hi Maurizio

I would give 'remodel -gated_clock' a shot, on top of 'set flatten model -gated_clock' which you're currently using.

Chrystian
maurizios
Posts: 8
Online: User is Offline
8/30/2007 7:32 AM  
I have did several trials. The bottom line seems to be the following;
- There is a clock gating structure in RTL Code
- I used the flattening option "set_flatten_mode -gated_clock"
- The gating elements are properly mapped in both golden and revised netlist.
When I am trying to diagnose a not-comparing points the cause of miscomparison seems to be the fact that for golden netlist clock itself and gating element are in the fanin cone but this is not true for revised netlist ( see line below0):
There are extra but mapped key points in this logic cone
================================================================================
ID Type Name
--------------------------------------------------------------------------------
(G) + 63763 'DLAT' /i_nocino_core/i_cpu_domain/i_VCPU_ClkCtrl/i_GrappaRefClkGate/Enable_Latch_reg
(G) + 63978 Nocino_analog_top:'PIN' /i_nocino_core/tvdd_domain0/i_nocino_analog_top/SCK
================================================================================

The tool finds then a failing pattern by applying a 0 to SCK
Does anybody have an idea why this is happening?
Thamks
Maurizio
maurizios
Posts: 8
Online: User is Offline
8/30/2007 10:18 AM  
Hi
eventually I came across the issue.
It was a Verilog construct not "particularly good" as :
always @(posedge clk or negedge rst_n)
if ( rst_n == 0 )
begin
...
end
else if (clk == 1)
begin
..
end

By changing to a more regular construct :
always @(posedge clk or negedge rst_n)
if ( rst_n == 0 )
begin
...
end
else
begin
..
end
it started to behave correctly. It looks the clause
else if (clk == 1)
is interpreted by the tool as a mux on the clock to the D input of the FF.

Maurizio
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Forums > Digital IC > Formal verification > Issue with gated clock


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