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Subject: RTL vs. gate netlist verification mapping problem
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alihusaini
Posts: 5
Online: User is Offline
1/16/2008 8:21 AM  
hello people,

I am doing RTL vs. gate netlist verification. I used "vif2conformal" tcl script in synplify pro to convert the verification file (.vif) obtained from synplify to conformal readable files( it generates many others .vtc, .vmc, etc.).
My problem is that the main dofile for conformal (i.e. .vtc file) calls anothers generated dofile file (.vmc mapping file). This .vmc file consist of mainly memories and some DFF (nearly 242735 lines) and i wish to bypass this map file by first black boxing the m/m and secondly "renaming" the DFFs.
The black boxing is done but i am not able to use the "add renaming rule" comand. I am attaching the extract from .vmc file in mail which i need to rename for fast processing.

Hope (and wish) that  if any of you could take some precious time out and help me doing so.

Thanks and regards,
ali.

wish that sometime i too reach a stage to help others :+)

Attachment: map.txt

croy
Posts: 54
Online: User is Offline
3/17/2008 9:17 AM  
Hi

Please open an SR through http://sourcelink.cadence.com if this is still an open issue.

Chrystian
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Forums > Digital IC > Formal verification > RTL vs. gate netlist verification mapping problem


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