Hi,

I have performed Equivalence check (Using Encounter CONFORMAL (R)  Version 07.10-s140 )  between two verilog netlists generated by two different Quartus Versions targeting two different ALTERA devices.

 Devices Used :

• Stratix ( EP1S30F780I6) used for Revised netlist.
• Stratix II ( EP2S30F484I4) used for Golden netlist.

 Quartus Versions Used:

* Version 5.1 Build 176 10/26/2005 Service Pack 0.15 SJ ( For Stratix, Revised Netlist ).
* Version 6.1 Build 201 11/27/2006 SJ Full Version ( For STRATIX II, Golden Netlist)

Here netlist refers to Verilog Formal verification O/P Netlist  generated by Quartus tool on both sides.

There were non-equivalences generated due to architecture differences of different devices. Please note that there were  no changes in RTL's used, except the modification done on soft macro's with respect to device.

Observation of Errors:
STRATIXII device drives clock output of the PLL to CLOCK CONTROL BUFFER which in turn drives clock output into design blocks. Whereas STRATIX device  doesn’t use CLOCK CONTROL Buffer and clock output of PLL is directly driven to design blocks.

I understood that there will be differences; however i would like to know if there are any Conformal Settings or Commands related to these devices to resolve non equivalences.

Please find the script attached that was used for performing LEC Verification. Extract of Non-equivalence error report is attached as well .

Kindly give your suggestions and comments and feel free to ask me if you require further inputs.

Thanks in advance,
Warm regards,

Dina.