Wednesday, December 03, 2008     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Digital IC > Formal verification

Subject: LEC Hier-compare when sub modules have extra port in Revised Design!!
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
chirag
Posts: 3
Online: User is Offline
5/29/2008 10:23 PM  
Hi, We have a question regarding LEC. We have asked our syntesis tool to introduce clock gating cells while preserving limited hierarchy(ie. our chip has 10 modules and each module has 100 submodules. We are preserving hierarchy of our 10 modules while flattening them inside).(we want to run Conformal on each of the 10 modules separately). Synthesis tool has mostly placed clock gating cells inside the module hierarchy. For some modules, it has placed a clock gating cell outside the module. Output of these clock gating cells are going inside the modules i.e. an extra clock port is added in revised design. How to handle such a scenario. 'ADD ECO PIN' is not enough because we need to tell Conformal that extra port is the output of clock gating cell. - Thanks
croy
Posts: 54
Online: User is Offline
5/30/2008 1:23 PM  
Hi Chirag

Funny you sent this question in: I just started testing an enhancement R&D implemented to deal with this kind of situation!

Can you please contact me directly? My email username is same as on cdnusers.org, just add "at cadence dot com"

Chrystian
adudyala
Posts: 3
Online: User is Offline
7/14/2008 3:06 PM  
Hi Chrystian,

Do you have any update on this issue. I had to jump through a lot of hoops to get my designs with extra ports (added by PD) to compare.
Any upate will be appreciated.

Thanks,
Amar.
croy
Posts: 54
Online: User is Offline
7/14/2008 3:54 PM  
Hi Amar

The command you're looking for is 'move instance down', available in 07.20-s300. You can use it to move that clock-gating latch in the hierarchy.

For ports inserted by clock-tree synthesis though you would use:

write hier dofile -noexact_pin_match -constraint -extract_clock

If you have feed-throughs you would add -input_output_pin_equivalence as well.

If you're going to run dynamic hierarchical verification (run hier_compare) then you would add -run_hier too.

Chrystian
Posting to forums is available to community members only.
Login or Register
Forums > Digital IC > Formal verification > LEC Hier-compare when sub modules have extra port in Revised Design!!


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.