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Forums > Digital IC > Floorplanning, Place and route

Subject: user opinion on SOCE hold fixing in 130nm and 90nm design
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lisiang
Moderator
Posts: 48
Online: User is Offline
2/13/2006 11:16 AM  
We ran into some problem in hold fixinng in SOCE, not abel to fix all the violations. STA using Prime Time reported more violations than SOCE.

Thanks.

li siang
BobD
Posts: 80
Online: User is Offline
2/17/2006 2:16 PM  
Hi lisiang,

Did SoC-E report hold violatons remained after running hold fixing?

ie, do you think it was purely a timing correlation issue -or- a quality of results issue as well as a timing correlation issue?

Thanks,
Bob
lisiang
Moderator
Posts: 48
Online: User is Offline
2/17/2006 2:25 PM  
it is more of timing timing correlation issue. By default, PT report both setup and hold violation in OCV mode, ie for setup, fast slew prop. to the lauching flop and slow slew prop. to the capturing flop. SOCE timing optimzation (optDesign) was not able to handle both fast and slow slew prop. in the same run.

li siang
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Forums > Digital IC > Floorplanning, Place and route > user opinion on SOCE hold fixing in 130nm and 90nm design


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