Tuesday, January 06, 2009     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Digital IC > Floorplanning, Place and route

Subject: Routing of large number of preplaced blocks
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
cdnuser78
Posts: 3
Online: User is Offline
2/14/2006 9:52 PM  
Hi,

I have a problem in which I need to route a large number (around 1000) of logic and memory blocks in a structured ASIC. Each logic block may have variable number of inputs and outputs (around 40 I/Os) that need to be routed. Each of the memory blocks has around 90-100 I/Os. Here are my questions:

1. Can NanoRoute Ultra handle a problem of this nature? Can it give an efficient solution or is it not really tuned for such problems?

2. What input format of the design does the router require? Are there any restrictions on where the pins of each block should be located? Is the router capable of using metal layers that have been utilized within a block layout?

3. Can the router also add buffering for high fanout/long nets? Can it make use of preplaced buffers?

Thanks very much. Greatly appreciated.
elvis
Posts: 13
Online: User is Offline
2/15/2006 11:28 AM  

Hi CDNUser78,

1. Can NanoRoute Ultra handle a problem of this nature? Can it give an efficient solution or is it not really tuned for such problems?

>>> That is a lot of memories design and I do not have the experience with that quantity. I would suggest running trial route first to make sure congestion issues are solved at the global route (floorplan) phase rather than wait for the detail routes. I have routed a design with Nanoroute that has 300+ memories with similar amount of memory pins without a problem.

2. What input format of the design does the router require? Are there any restrictions on where the pins of each block should be located? Is the router capable of using metal layers that have been utilized within a block layout?

>>> The input to nanoroute is DEF. I'm not sure about utilizing metal layers within the block. My guess is that since the LEF abstract is modeled as routing blockage that this is not possible. Maybe if you use GDS? Just a guess.

3. Can the router also add buffering for high fanout/long nets? Can it make use of preplaced buffers?

>>> This step is done by optDesign during physical synthesis. I don't think nanoroute will add buffers, though during SI repair nanoroute will work with Celtic in SoC-E to automatically insert buffers to eliminate SI issues.

Hope this helps.

Elvis
Posting to forums is available to community members only.
Login or Register
Forums > Digital IC > Floorplanning, Place and route > Routing of large number of preplaced blocks


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.