Tuesday, January 06, 2009     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Digital IC > Floorplanning, Place and route

Subject: Excluded pin during CTS
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
DN
Posts: 10
Online: User is Offline
2/23/2006 2:49 AM  
During CTS-run I've defined my clocktree as below:

AutoCTSRootPin TIMMCORE/u_core/u_coss/u_efc/u_fb_fs/f_wre_reg/Q
MaxDelay 7.0ns # set_clock_latency
MinDelay 6.7ns # default value
MaxSkew 300ps # set_clock_uncertainty
SinkMaxTran 900ps # set_clock_transition
BufMaxTran 900ps # set_clock_transition
Buffer dly1x3pdv dly2x3pdv dly2x8pdv dly3x3pdv
RouteType standard_clk
AddDriverCell cnbfx6pdv
PadBufAfterGate NO
NoGating NO
DetailReport YES
RouteClkNet YES
PostOpt YES
ExcludedPin
+ TIMMCORE/u_core/u_coss/u_efc/u_fb_fs/loc_tdo7_reg/TI
LeafPin
+ TIMMCORE/u_core/u_coss/u_efc/u_flash/WRE
END

But after CTS, the delay from the clock root to */TI
as same as the delay to the */WRE. My expecting is that the */TI pin should be excluded from the clocktree.

Ps. I'm using (cadence_fe 04.20-s315_1_USR2 )
DN
Posts: 10
Online: User is Offline
2/24/2006 4:40 AM  
I've just found that when you define (SetDPinAsSync YES) in the CTS-configuration file then it works.

From user guider
SetDPinAsSync YES | NO
Controls whether CTS automatically treats the D-pins of flip-flops as synchronous pins.

D-pins include

Data pins

Enable pins

Scan-in pins

Scan-enable pins

Synchronous set and reset pins

Default: If you omit this statement, CTS treats the D-pins of flip-flops as excluded pins. That is, CTS does not treat the pins as synchronous pins.
mohanch007
Posts: 52
Online: User is Offline
3/16/2006 9:11 PM  
Hi, Let me add few more comments on your topics,
The alternative way other then adding in script file is by setting the same in CTSMode "setCTSMode -setDPinAsSync " before loading ctstch script file.

Then this is global for all the other CTS trees.
Its allways adviceble to set soft rule for Preferred layers like avalable top metals (M5 , M4 ) in setCTSMode command .
like ( setCTSMode -topPreferredLayer M4  -bottomPreferredLayer M3 ) .
BTW how was your correlation of skew and delay between clk- route only and post route phase.

Regards,
Mohan
Posting to forums is available to community members only.
Login or Register
Forums > Digital IC > Floorplanning, Place and route > Excluded pin during CTS


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.