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EngHan
Posts: 65
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3/06/2006 11:45 AM
Hi, Would like to know how the following can be handled in Encounter flow. The data path is from a FF to another FF, and both FF are clocked by the same clock. In the data path, there is an OR gate. One of the input of the OR gate is from a clock source. The other input of the OR gate is data. As the OR gate is part of a clock network, the placer does not optimise it. Hence, during optDesign, due to the high-fanout of the OR gate, the delay of the OR gate is 200+ns. This result in a huge violation, and the QOR become bad. I have tried to use "setAnalysisMode noclksrcpath", but since the source of this path is data, the option does not effect. I workaround by setting a multicycle path from these 2 FFs during physical synthesis, and then remove it before clock tree synthesis. However, is there a better solution for this type of design? Thanks. Regards, Eng Han

mikenaustin
Posts: 1
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3/08/2006 1:59 PM
Hello Han, IF the output of the OR gate is clock and not data, the placer needs to know that it is a clock gating cell. You must do two things prior to placement and optimization: 1) specifyClockTree -clkFile clock_spec.cts 2) setPlaceMode -clkGateAware This should help the placer to try and find an optimal placement for the OR gate relative to it's leaf cells. IF the output of the OR gate is to a data pin, it should still see the timing path and optimize it. Please let us know if this helps. Best Regards, Mike Jacobs Cadence Design Systems

EngHan
Posts: 65
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3/09/2006 10:20 AM
Hi Mike, The tricky thing is that the output of the OR gate is both clock and data. One experienced AE advice me that the way to handle this is to use "setExcludeNet" command. I think the command is a good workaround. However, I am not using it now as the OR gate is a synthesized gate, and thus the net name will change with every new synthesized netlist. I should have fixed the RTL to fix the name of the net (or the OR gate), but I have yet to do this... Regards, Eng Han

mohanch007
Posts: 52
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3/15/2006 12:01 AM
Hi , Let me share my view on the above issue, I divide this in two two topics like FE-CTS and FE-IPO. In the Case of FE-IPO as we know that The opt command does not affect the Clock nets. In your case "OR" gate has such problem. So you can not use if it is recognised as a Clock path. Work around : Try to make a special SDC with out clock defination and run "optDesign" command for correcting only DRVs by using only "MaxFanout" switch . FE-CTS handling case : use "fixClockExcludedNetDRV" after exclusing data pin . (or ) We can perform hight fanout synthesys (FE-CTS) , need to prepare new ctstch clock specification file and specify a clock defenation at the output of "OR" gate and run "ckSynthesis" . Note on this run : we should not give any clock attributes on such nets and NO route. use : -dontFixAddedBuffers ,"-noAddClockRootProp" "-noFixedNonLeafInst" and Route Clk NO (spec file)etc . If you have trace problem on OR gate use "set _case_analysis" in spec file . Regards, Mohan Ch

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