Dear Giohdl,
Delighted seeing your explanation.
In general in system mode all the critical paths are synchronous in nature (only rising edge-triggered )
Aside please let me add my comments on CTS constraints file. (design.ctstch)
Things to be considered
1. Skew alignment (MaxSkew) between clock groups (CLK,CLK_NEG,CLK_END).
2. Ideal CLK MaxDelay (setup) and MinDelay (hold) (set_clock_latency).
3. handling generated clock in CTS by hierarchically CTS ( preserve pin)
4. Skew alignment for Rising Sync Pins and Falling Sync Pins
Out of the above 4 topics I will help you in 1 and 3 which are the two different approaches.
1. Skew alignment (MaxSkew) between clock groups (CLK,CLK_NEG,CLK_END).
ClkGroup
+ clockRootPinName
+ clockRootPinName
You can use the ClkGroup section to balance clock skew between two or more clock trees.
Alternatively, you can balance skew as follows:
* run CTS once
* specify MinDelay constraints for all clock trees with the largest clock phase delay, and
* rerun CTS. However, using ClkGroup often provides better results.
It is recommended to use ClkGroup with MinDelay 0 if you need to balance clock skew among multiple clock trees.
- Clock Tree Specification File Example
##------- RouteType
RouteTypeName double_space
TopPreferredLayer 7
BottomPreferredLayer 5
PreferredExtraSpace 1
NonDefaultRule double_width
End
##------ Clock Group (Balance skew between two clock trees)
ClkGroup
+ CLKROOT1/Z
+ CLKROOT2/Z
##------ CLK1 -------
AutoCTSRootPin CLKROOT1/Z
MaxSkew 300ps
MinDelay 0.000ns
MaxDelay 10.000ns
SinkMaxTran 500ps
BufMaxTran 500ps
MaxFanout 32
addDriverCell BFX8
LeafPin
PreservePin
+ BLOCK1/MODULE4/CELL4/Z
End
Preserves the net-list after the specified pin.
FE-CTS builds other portions of a clock tree in such a manner as to balance clock skew with
the preserved logic.
See Figure for Ex. of PreservePin
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