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Forums > Digital IC > Floorplanning, Place and route

Subject: How to make nanoroute understand "USEMINSPACING"
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EngHan
Posts: 65
Online: User is Offline
1/10/2007 11:27 PM  
Hi,

I am facing the following issue for quite sometime. Wonder if anyone is also facing the issue and has a solution?

I have "USEMINSPACING OBS OFF ;" in the technolog lef. However, nanoroute places alot of wire at min spacing to "thick blockage". VerifyGeometry is able to detect these DRC, but nanoroute does not detect the violations. It is quite a pain to clean these violations post-layout.

Anyone also face this issue? Thanks.

Regards,
Eng Han
Stalker
Posts: 24
Online: User is Offline
1/11/2007 1:53 AM  
Hi,
Try the following:
setNanoRouteMode -quiet drouteUseMinSpacingForBlockage false

If the "thick blockage" is memory, those min_step violations you see maybe false, because LEF doesn't show the real route of the memory, and the blockage you see is not "thick". The final DRC checks are performed with GDS and not with LEF
Maxim R.
EngHan
Posts: 65
Online: User is Offline
1/14/2007 9:44 PM  
Hi Stalker,

Thanks for the tip. I try the setting, and it works around 95% of the time! For example, if I don't use this setting, I get 100 violations. If I use the setting, I get much less violations, about 5.

With or without the settings, nanroute finished with 0 violations. Something else is still strange...

Regards,
Eng Han
lisiang
Moderator
Posts: 48
Online: User is Offline
1/15/2007 7:49 AM  
It is possible that Nanoroute still did not see those 5 violationsblockages as fat blockages. In lef5.6 syntax, you can make those blockages with the spacing you want. You can check the lef reference doc. As for why Nanoute did not see the violation, one possible answer is that those are power wire with slotting and the lef is modeled it as thin blockage.

li siang
EngHan
Posts: 65
Online: User is Offline
1/15/2007 7:50 PM  
Hi,

I look at the remaing violations and observed that they are of the same type.

The violation is between routed M4 with M4 pin (from the lef). The M4 pin is a power net. When this M4 pin tape to a wide M3 pin (also in the lef), spacing from the VIA34 has to obey wide metal spacig. It look like nanorouter does not understanding this while verifyGeometry detct the error.For now, I am not sure if nanoroute is correct or verifyGeometry is correct.

Regards,
Eng Han
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Forums > Digital IC > Floorplanning, Place and route > How to make nanoroute understand "USEMINSPACING"


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