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Subject: How to generate PinText for Chip level?
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DN
Posts: 10
Online: User is Offline
3/13/2007 2:39 AM  
Hello,

I'm trying to find a way to generate  a PinText (call_text) from FE.
Until sofar I can get the locations + layer of Pads which have really Pin/Net connections. 
For example well for  'pad_VDD_IO_1' but not for 'pad_VDD_CORE ' because lacked of a net connection.
 "vddi" is a global pwnet and connected to vdd by using wildcard *.

In my netlist:

  vddi pad_VDD_CORE (  );
  vdde3v3co pad_VDD_IO_1 ( .vdde3v3(SYNOPSYS_UNCONNECTED_1) );


If you have some suggestion/advice pls send me. Thanks.
EngHan
Posts: 65
Online: User is Offline
4/13/2007 2:24 AM  
Hi DN,

What I did is to dump out a DEF before placement. The def has all the pad and macro, but no std cell. I then rip out all the pads statement from the def file. I then use this info to determine the bonding points. With this information, I generate three files:

1. A TCL that will add the bond pads (addInst and placeInstance commands) and pin text (addCustomText command) to the layout
2. Generate bonding netlist that will be needed by the assembly house
3. Two files that voltagestorm needs to indicated the location of power and ground source.

All the above can be scripted, and is run from encounter with something like "exec scripts/go.csh".

Regards,
Eng Han
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Forums > Digital IC > Floorplanning, Place and route > How to generate PinText for Chip level?


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