Tuesday, January 06, 2009     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Digital IC > Floorplanning, Place and route

Subject: COND expressions in SDF files
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
clsantos
Posts: 31
Online: User is Offline
6/19/2007 3:26 PM   
Hello,

When a timing arch of a cell has COND expressions, what delay value of these conditional
expression is used for setup and hold analysis?
Considering the example below, what delay value would be used by, e.g., CTE to report delay of this cell considering timing arch C -> Q?

#####
(CELL
  (CELLTYPE  "ON21LX1")
  (INSTANCE  gbl_slave_test/g310)
  (DELAY
   (ABSOLUTE
    (IOPATH C Q  (0.076::0.076) (0.047::0.047))
    (COND ((A==1'b1)&&(B==1'b1)) (IOPATH C Q (0.076::0.076) (0.047::0.047)))
    (COND ((A==1'b1)&&(B==1'b0)) (IOPATH C Q (0.078::0.078) (0.057::0.057)))
    (COND ((A==1'b0)&&(B==1'b1)) (IOPATH C Q (0.079::0.079) (0.076::0.076)))
    (IOPATH B Q  (0.106::0.106) (0.092::0.092))
    (IOPATH A Q  (0.082::0.082) (0.076::0.076))
    )
   )
 )
#####

Can anyone help me?

Regards,
Cristiano.
lisiang
Moderator
Posts: 48
Online: User is Offline
6/19/2007 4:38 PM  
the worst case number will be used (in this case 0.079 for rise & 0.079 for fall) unless you have a set_case_analysis statment in the sdc file to set the state of pin A or B.

li siang
clsantos
Posts: 31
Online: User is Offline
6/20/2007 6:31 AM  
Thanks again lisiang.

Will timing analyzer use worst case delays for setup analysis and best case for hold analysis?

What is the purpose of the delay values in the right side of "IOPATH C Q"?

What delay value will be used in case of ((A==1'b0)&&(B==1'b0))?

Cristiano.
lisiang
Moderator
Posts: 48
Online: User is Offline
6/20/2007 11:14 PM  
Sorry i was wrong about the 0.079. If logic state of A OR B is unknown. STA uses the IOPATH number, 0.076 for max path and 0.047 for min path.   If A=1 && B=1 (set_case_analysis) then max path check will use 0.076 and min path check will use 0.047.  Typicallu max path is for setup check and min path is for hold check.
grasshopper
Posts: 48
Online: User is Offline
6/27/2007 5:17 AM  
One clarification dsantos,

Most tools will use ALL arcs, and take the max delay of them(min for hold checking). If, however, one of the inputs of the gate was a constant(hard-wired or case analysis), then arcs whose "COND" function resolved to 0 are disabled. Also, if the constants on the gate inputs narrow the choice of COND expressions down to a single one, then the default "COND-less" arc is disabled. Hope this helps.

regards,
gh-
Posting to forums is available to community members only.
Login or Register
Forums > Digital IC > Floorplanning, Place and route > COND expressions in SDF files


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.