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Forums > Digital IC > Floorplanning, Place and route

Subject: Info required on IO Assignment methods
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bsriram83
Posts: 1
Online: User is Offline
7/11/2007 10:46 PM  
Hi to all,

My name is Sriram, I need some help from u.

Presently i am working on IO pad assignment and
placement for a Chip. How can i arrange different IOs and How can i decide thePower and Ground pads requirement and How can i teke care about ESD, SSO and other things if any.
For this i need some good article and guidance from u.

Thanks in advance...

Have a nice day....

Sriram

+91 9848382342
lisiang
Moderator
Posts: 48
Online: User is Offline
7/19/2007 10:38 AM  
what you are asking is a design issue and it is not related to the tools. This is not the right place to ask this type of question.

ESD is related to your pad design and SSO is related to type of I/O and speed. And both of then are related to process too. You need to work with your foundry/circuit engineer to determine how many power/gnd pad to signal pad ratio for SSO and you will need ESD protection for all the pads.

li siang
EngHan
Posts: 65
Online: User is Offline
7/19/2007 6:17 PM  
Hi Sriram,

You can get many of the answer from the I/O pads data sheet. It will tell you how many pad-ring ground/power pads are needed. It is related to the number of output I/O pads you used, and the max distance from any pad to a pad-ring ground/power pads.

It is always necessary to read the I/O pad datasheet. For example, you might also have special pad, like osc pad, USB pad, PCI pad, analog power pad, power pad for efuse/flash/etc etc. There are always special layout requirements.

As for core power pad, a short answer is to run powermeter/voltagestorm to analyze IR drop and max current flow. As LiSiang point out, it is process and design related. Perform some early analysis and develop your own rule of thumb for a particular process and design. For a start, read the datasheet to get the max current a power/ground pad can provide. Then ask the designer what is the expected power consumption. Then multiple this number by a factor (you have to figure out this factor base on the experience you interact with the design team. Also, note that worst power usually occur during test mode). For power stripping, start from at least 20% of the core area is covered by metal stripe (excluding M1 stripe).

Regards,
Eng Han
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Forums > Digital IC > Floorplanning, Place and route > Info required on IO Assignment methods


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