Tuesday, January 06, 2009     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Digital IC > Floorplanning, Place and route

Subject: clock tree levels and gating
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
aus_amx
Posts: 2
Online: User is Offline
8/25/2007 4:52 PM  
Hi,

I have tried SOC62, and have noticed that as soon as I add clock gating in RC, the number of clock tree levels blows out, in my case from 6 levels to 22.
I have tried all sorts of options and commands in the clock spec file, but the levels don't change much.
The gating happens very close to the root, and one would think that it should add just a couple of extra levels not 15.
What's worse is that with gating the skews also become a lot worse.

Is this normal?

Thanks
AA
Kari
Posts: 81
Online: User is Offline
8/27/2007 2:55 PM  
Hi AA,

When you place the design, try using setPlaceMode -clkGateAware 1. Hopefully a better placement of your clock gating logic will lead to a better tree when you get to CTS.

- Kari
aus_amx
Posts: 2
Online: User is Offline
8/27/2007 4:27 PM  
Hi Kari,

Yes I have used this option as well.
I am using the -keepPorts and fences to keep the ports of a block intact.
Could this be causing the problem?

Regards
AA
Kari
Posts: 81
Online: User is Offline
8/30/2007 12:21 PM  
Hi AA,

In re-reading this thread, I realized you were talking about RC. I don't have much experience there. I was thinking in terms of FE. Hopefully there is an RC expert around that may be able to offer some advice.

If the -keepPort switch you mention IS in FE, then try a run without it and compare the results.

- Kari
mboudreaux
Posts: 11
Online: User is Offline
3/26/2008 2:16 PM  
I have this issue as well... I have since learned I needed to manually build the clock tree to avoid this issue. I agree - it is specific to gated clock trees where the gate is close to the root.
BobD
Posts: 80
Online: User is Offline
3/27/2008 11:17 AM  
Hi mboudreaux,

Have you tried to leverage SoC-Encounter's Integrated Clock Gating Cell cloning capability ("ckCloneGate")? In scenarios where there are multiple levels of clock gating with different enable signals, "setPlaceMode -clkGateAware true" has limited effectiveness in my experience.

Thanks,
Bob
Posting to forums is available to community members only.
Login or Register
Forums > Digital IC > Floorplanning, Place and route > clock tree levels and gating


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.