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Forums > Digital IC > Floorplanning, Place and route

Subject: remaining transition violations on clock nets
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jaheira
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11/12/2004 7:22 AM  
I have macro cells in the design that have transition limit on a clock pins that is much lower than standard cells. In the ctstch file I have to define transition requirements SincMaxTran that is appropriate for standard cells but higher than that of the macro cells. As a result a few transition violations remain on clock nets connected to the macro cells - Cadence CTS optimizes transition based on a requirement in ctstch file without considering lib files. Do you have any automated solution to fix remaining transition violations, besides what I currently have in the flow is a fix by "Interactive ECO" ?
kevink
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11/16/2004 12:24 PM  
This is what the MacroModel syntax is created for. In your CTS constraints specification, you can specify a min and max rise/fall delay on the macro port (for all instances of a macro) or pin (instance specific). The syntax is:

MacroModel port cellName/portName maxRise minRise
maxFall minFall inputCap

For example:

MacroModel port myMacro/clk 10ns 5ns 12ns 7ns 20pf

I have found that any units are OK but you must specify SOME unit (ps, ns, etc).

Kevin
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Forums > Digital IC > Floorplanning, Place and route > remaining transition violations on clock nets


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