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Forums > Digital IC > Floorplanning, Place and route

Subject: using Low Vth and Mid Vth library
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sundaresan
Posts: 5
Online: User is Offline
10/25/2007 10:02 PM  
Hi,

In my  design, i have to use low Vth library for one particular Block B1 alone for better timing.
The other block B2 should use only Mid Vth library cells.

But i found that Soc encounter is picking up Low Vth cells for the block B2 also, during Timing optimiztion, which is not expected.

How to restrict the usage of Low Vth cells and Mid Vth cells for blocks B1 and B2 respectively?


thanx
sundar
ssunder@sioptical.com
Posts: 24
Online: User is Offline
11/06/2007 6:57 AM  
If the requirements are so stringent - then perhaps a hierarchical flow would be a way to do it. Are your constraints all clean?

Sanjay
bougantp
Posts: 19
Online: User is Offline
11/06/2007 7:19 AM  
For my understanding on the way Encounter works , there is no real way to do what you want, optDesign will use all available cells to fix timing issues, all means all available VT cells.
optLeakage goal is to work on DB trying to switch lowVT cells to highVT cells.
Please try it after optDesign -setup.
Personnaly I use it and the gain of leakage is very good (The CPU runtime is not negligeable...).
Another impact of this command, it help Hold fixing, so I use it just before optDesign -hold.

Pat.
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Forums > Digital IC > Floorplanning, Place and route > using Low Vth and Mid Vth library


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