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Forums > Digital IC > Floorplanning, Place and route

Subject: how to accelerate placement in large design?
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Dota
Posts: 7
Online: User is Offline
11/09/2007 1:10 AM  

When doing floorplan in a large design, We partition top and estimate whether floorplan is satisfied or not. So place and route become necessary step. My problem is placement is so slow because of many gates in partition. how to solve it ?
elvis
Posts: 13
Online: User is Offline
11/09/2007 8:52 AM  
 

When running placement for this you can use the floor plan mode placement (setPlaceMode -fp) which runs a quick non-timing driven placement.     This works great for getting your instances placed into the fences which will be later refined after partitioning.

You could also experiment w/ cluster placement which does netlist clustering to reduce the instance count.  

How large is your design?

Regards,
Elvis
Dota
Posts: 7
Online: User is Offline
11/09/2007 7:50 PM  
3x elvis. my design is about 20 million gates and 11 partitions. Does encounter only place instance relative to port of partition, not more placement work in partition. cluster place sounds interesting, could you tell me more about it or some documents.
bougantp
Posts: 19
Online: User is Offline
1/02/2008 8:01 AM  
When you said that your design is about 20 millions gates, In fact it is more intersting to give the number of instances, Which is exactly what the placer has to deal with.

On my side I play with chip which have 3.5 millions instances, Timing driven placement is about 7hours. I aggree it is long but not killer.
At early stage, I deal with what Cadence call Black Blob.
For submodule inside each partition, I replace the full gate level netlist by a dummy one (The blob netlist). Unstead of standard cells, the blobs contains kind of super cells, which is bigger than the standard cells. You can attach hard macro to your blob.

With such tricks my placement tooks less than 2hours, which is definitely better and allow me to make several iteration per day...

Once It seems OK I switch back to the full gates placement.

Be carrefull the Blob definition need a GXL license.

Pat.
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Forums > Digital IC > Floorplanning, Place and route > how to accelerate placement in large design?


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