agruebl
Posts: 4
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| 11/14/2007 8:49 AM |
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Dear community,
my clock signal is connected to the clock network on the one hand. On the other hand it is connected to a module's input. Within this module the signal is always used as a data signal (chip is switched to different mode of operation for this).
This module contains logic, therefore CTS traces through the input ports. AFAIK tracing can only stop at top level ports or leaf cell pins.
Is there any way to make CTS stop tracing at the module's input port (like ExcludedPin/ExcludedPort - which don't work)?
Many thanks in advance for your suggestions!
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raul63
Posts: 0
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| 11/14/2007 5:35 PM |
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Hi agruebl,
You need the "LeafPin" command in your ".ctstch" file on the input pin of the first device(s) in your module.
If you look at the "Encounter User Guide" (soceUG.pdf), "Synthesizing Clock Trees" (Chapter 11),
Product Version 6.2.2 (SOC6.2), August 2007, on Page 477, you will see the following:
LeafPin
+ pinName rising | falling
+ …
Marks the input pin as a “leaf” pin for non-clock-type
instances, stops tracing, and balances clock skew.
Note: Use the LeafPin statement only with input pins.
CTS ignores LeafPin statements that are associated
with output pins.
Choose one of the following:
rising - CTS treats the input pin as a risingedge-
triggered flip-flop clock pin.
falling - CTS treats the input pin as a fallingedge-
triggered flip-flop clock pin.
Here's a real life example. These are input pins of devices where clock was stopped
from tracing through combinational logic gates.
LeafPin
+ i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/a1
+ i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/a2
+ i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/b1
+ i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/b2
Regards - R.M. |
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raul63
Posts: 0
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| 11/14/2007 5:40 PM |
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Hi agruebl,
My previous example should have had the word "rising" at the end of each LeafPin declaration:
LeafPin
+ i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/a1 rising
+ i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/a2 rising
+ i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/b1 rising
+ i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/b2 rising
Regards - R.M. |
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agruebl
Posts: 4
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| 11/15/2007 2:21 AM |
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Hi raul63,
many thanks for your answer! Unfortunately it doesn't fix my problem... What I did not mention is that I switch (not regularly but I do ;-) ) between cell libraries and the input pins have different names in the diff. libraries.
So I wanted to have a somewhat technology independent solution and define the module's input port as a leaf. Consequently CTS would have to either:
* automatically treat all directly connected cell inputs (inside the module) as leaf pins, or
* treat the module input as a leaf.
The second point is probably impossible because CTS wouldn't "know" where to stop tracing when using this module port without physical pins. So the question is wether the firts point is feasible.
One (rather time consuming) solution I am currently thinking about is to extract the names of the leaf pins connected to the module port using a TCL script and to insert these names into the ".ctsh" file using a PERL script or something.
Hope this describes my problem a bit more precisely... any ideas? ;-)
Regards,
Andreas
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raul63
Posts: 0
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| 11/15/2007 9:14 AM |
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Hi Andreas,
I have never tried what you are attempting to do, however,
in the Encounter User's Guide, there is the following command,
which I am assuming would declare a module port as a "LeafPort":
LeafPort
+ portName rising | falling
+ …
Marks the port as a “leaf” port for non-clock-type
instances, stops tracing, and balances clock skew.
Choose one of the following:
rising CTS treats the pin as a rising-edgetriggered
flip-flop clock pin.
falling CTS treats the pin as a falling-edgetriggered
flip-flop clock pin.
From Encounter User Guide
Synthesizing Clock Trees
August 2007 Product Version 6.2.2, p. 478
Regards - R.M. |
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bsg
Posts: 2
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| 11/15/2007 10:15 AM |
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Hi Andreas,
You do not need to write a perl script. What you can do is to load the database into FE.
Under the top menu "Tools", open up the design browser, (let say that hierarchical module and port name is
ata_top/atahost1/clk_i),
fill in the name in and click 'Enter', it will show all the instance with pin that connect to this input port.
Save the file using File => Save As.
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eminemshow
Posts: 75
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| 11/15/2007 7:14 PM |
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agruebl:
You can use 'dbGetHTermByName' to get the hierarchical term, and then use 'dbHTermNet' to get the net. Finally use the db command to get all downstream inputs of that net. all you need is to define the module port pattern. And then use some TCL to output the leafpin definitions.
Best Regard
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agruebl
Posts: 4
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| 11/16/2007 12:41 AM |
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@raul63:
I have tried this but CTS gives the warning
**WARN: The LeafPort + sn_top/rx_delay/rx_del0_0_/in is an invalid name.
for every hierarchical port that I specify (product version 5.2.6). This option seems a bit useless, provided it accepts only top level ports as arguments?
@bsg:
... I'm trying to avoid GUI usage in our design flow (after floorplanning) ;-) Unfortunately some instance names do change after intermediate re-synthesis runs.
@eminemshow:
This seems to exactly solve my problem. But my software doesn't recognize the db commands. Are these OpenAccess commands (not available here)? I couldn't even find them in the SKILL manual..
Anyway, I will try to do this all in TCL using get_pins and all_connected etc. Thanks for the hint!
Thank you all for you help! Great forum! :-)
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BobD
Posts: 80
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| 11/16/2007 8:47 AM |
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This is an interesting thread- thanks for raising the question!
Here's some thought I have on what's been discussed:
(1) It looks like CTS doesn't offer an ability to stop on hierarchical module ports. In some ways, that's not surprising because a hierarchical module port doesn't necessarily have a physical location. If we're asking the tool to build a tree *to* the module port and it doesn't have a location, how should CTS know where to place the buffers? The intent may be to treat elements downstream from the hierarchical module port as a leaf (which sounds like what you're seeking to do), but it's not clear to me that everyone would expect this behavior every time.
(2) The leafPort option offers a way to specify a stop point based on the master cell name rather than the instance name (ie, "BUFX1/A" instead of "DTMF_INST/RESUTLS_CONV_INST/i0/A"). With a leafPort, you can therefore be more concise in the way you instruct the tool to stop based on cell-type rather than having to find and list every instance pin. Hope that makes sense.
(3) You might want to consider specifying these pins as "ExcludePin" rather than "LeafPin"- the difference being whether CTS balances to the elements inside the module or merely omits them from being sink targets.
(4) Regarding coming up with a scripted solution to the challenge of "how to find the instance pins driven by a hierarchical module port"- there are 3 options for db access in this area that I'll include examples of below.
Hope this helps
#FE-TCL style (available in all FE releases)
#userHTermSinks DTMF_INST/RESULTS_CONV_INST/clk
proc userHTermSinks {htermName} {
set returnList {}
set hterm [dbGetHTermByInstTermName $htermNam! e]
set net [dbHTermNet $hterm]
dbForEachNetInputTerm $net te rm {
set instName [dbTermInstName $term]
set instHInstName [file dirname $instName]
set termName [dbTermName $term]
set instTermName $instName/$termName
set hinstName [dbHInstName [dbHTermHInst $hterm]]
if {[string match $hinstName $instHInstName]} {
Puts "$instTermName"
lappend returnList $term
}
}
return $returnList
}
#CTE-TCL style:
#user_get_pin_sinks DTMF_INST/RESULTS_CONV_INST/clk
proc user_get_pin_sinks {hterm_name} {
set hinst_name [file dirname $hterm_name]
set sinks [all_connected [all_connected [get_pins -hierarchical $hterm_name]]]
foreach_in_collection sink $sinks {
if {[get_property $sink object_type] == "pin"} {
set sink_instterm_name [get_property $sink hierarchical_name]
set sink_inst_name [file dirname $sink_instterm_name]
set sink_hinst_name [file dirname $sink_inst_name]
if {[string match $sink_hinst_name $! hinst_name]} {
append_to_collection return_sinks $sink
}
}
}
query_objects $return_sinks
return $return_sinks
}
#dbGet style (available in SOC7.1.RTM):
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BobD
Posts: 80
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| 11/16/2007 9:07 AM |
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Oops- I forgot to click the "html" tab before posting the code example. Hopefully this will come through readably:
#FE-TCL style (available in all FE releases)
#userHTermSinks DTMF_INST/RESULTS_CONV_INST/clk
proc userHTermSinks {htermName} {
set returnList {}
set hterm [dbGetHTermByInstTermName $htermName]
set net [dbHTermNet $hterm]
dbForEachNetInputTerm $net term {
set instName [dbTermInstName $term]
set instHInstName [file dirname $instName]
set termName [dbTermName $term]
set instTermName $instName/$termName
set hinstName [dbHInstName [dbHTermHInst $hterm]]
if {[string match $hinstName $instHInstName]} {
Puts "$instTermName"
lappend returnList $term
}
}
return $returnList
}
#CTE-TCL style:
#user_get_pin_sinks DTMF_INST/RESULTS_CONV_INST/clk
proc user_get_pin_sinks {hterm_name} {
set hinst_name [file dirname $hterm_name]
set sinks [all_connected [all_connected [get_pins -hierarchical $hterm_name]]]
foreach_in_collection sink $sinks {
if {[get_property $sink object_type] == "pin"} {
set sink_instterm_name [get_property $sink
hierarchical_name]
set sink_inst_name [file dirname $sink_instterm_name]
set sink_hinst_name [file dirname $sink_inst_name]
if {[string match $sink_hinst_name $hinst_name]}
{
append_to_collection return_sinks
$sink
}
}
}
query_objects $return_sinks
return $return_sinks
}
#dbGet style (available in SOC7.1.RTM):
proc userGetHTermSinks {htermName} {
set hterm [dbGet -p [dbGet -p head.allCells.objType
vCell].hInst.hinstTerms.name $htermName]
set hinstName [dbGet $hterm.hInst.name]
Puts "[dbGet [dbGet -p $hterm.net.allTerms.objType instTerm].name $hinstName*]"
return [dbGet -p [dbGet -p $hterm.net.allTerms.objType instTerm].name $hinstName*]
}
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eminemshow
Posts: 75
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| 11/16/2007 9:55 PM |
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Bob:
I just attended the SOC-E 71 Release seminar. It is great that you give a living example of how to use dbGet.
Many Thanks!
Best Regard |
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agruebl
Posts: 4
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| 11/19/2007 1:53 AM |
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...and here's my solution. I've done it with Sy****ys-TCL and this code is called directly after Synthesis. A .ctsh file with a "special" format containing the hierarchical port definitions is parsed and the output is written to the .ctsh file used by CTS.
set repl_trigger "REPLACE_"
set rootpin "AutoCTSRootPin"
set infile [open $CTSINFILE]
set outfile [open $CTSOUTFILE w]
set data [read $infile]
set lines [split $data \n]
set replace false
foreach port $lines {
# parse input lines
set pstart [string range $port 0 7]
if {$pstart == $repl_trigger} {
# the port definitions following this line will be replaced
set replace true
set out [string range $port 8 end]
set outtype $out
if {$out != $rootpin} {
# the RootPin needs to be defined in the same line as the according statement...
puts $outfile
$out
}
} elseif {$replace == true && [string index $port 0] == "+"}
{
# replace port name with pin name(s)
set aport [string range $port 3 end]
if {[string index $port 1] == "i"} {
# replace input leaf pin names
set inpins [get_pins
-filter "@pin_direction == in" -hierarchical [all_connected [get_nets $aport]]]
set prefix "+
"
} else {
# replace output pin names
set inpins [get_pins
-filter "@pin_direction == out" -hierarchical [all_connected [get_nets $aport]]]
if {$outtype
== $rootpin} {
set prefix "$rootpin\t\t"
} else {
set prefix "+ "
}
}
if {[get_object_name [get_nets $aport]]
!= ""} {
foreach_in_collection pin $inpins {
set out "$prefix[get_object_name $pin]"
puts $outfile $out
}
}
} else {
# line not relevent - forward to output
set replace false
puts $outfile $port
}
}
As all regular code in the input .ctsh file is forwarded to the output file, hier. port definitions and correct pin definitions can be mixed. :-)
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mahecadence
Posts: 19
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| 11/20/2007 3:56 AM |
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Thanks for all
This info gave me a lot of new things about CTS |
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mahecadence
Posts: 19
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| 11/20/2007 4:00 AM |
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hi eminemshow
please can you tell me the difference between clock buffers and normal buffers |
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eminemshow
Posts: 75
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| 11/20/2007 5:23 PM |
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Posted By mahecadence on 11/20/2007 4:00 AM
hi eminemshow
please can you tell me the difference between clock buffers and normal buffers I think the main difference is that clock buffer & inverter have nearly equal rising & falling delay.
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mahecadence
Posts: 19
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| 11/20/2007 8:25 PM |
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| Thanks |
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lisiang
Moderator
Posts: 48
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| 11/21/2007 9:38 AM |
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without equal rise/fall delay, the duty cycle (started with 50/50) will get distorted going thru the unbalance buffer. It should bot affect the flops operation which trigger off the rising edge but some ram designs trigger off the falling edge. Inverter can slef-correct the unbalance rise/fall due to it inverted nature. So inverter is a better choice to use in a clock tree to prevent duty cycle distortion.
li siang
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