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Forums > Digital IC > Floorplanning, Place and route

Subject: timing critical design
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viswanadhbabu
Posts: 16
Online: User is Offline
1/07/2008 9:22 AM  
Hi all, Currently iam handling timing critical design in which if setup is optimised hold comes into picture and vice versa Can anyone help me in solving this KVB
mohanch007
Posts: 52
Online: User is Offline
1/08/2008 12:35 AM  
During Hold Optimization treat Setup nets as excluded

Or you can do only HOLD optimization using selected-Terms.

If you exclude setup nets and Select Only HOLD terms , If there is any common between hold and setup with be not optimized.

Hope it helps !!

FYI.

Ex. optDesign -postCTS -excludeNets

-Mohan
Kari
Posts: 81
Online: User is Offline
1/11/2008 11:59 AM  
Hi KVB,

The situation you describe can be very tricky. Sometimes you need to fix these paths by hand, and look further back along the path to find a place to fix one (setup/hold) that doesn't break the other. If there really is no way to fix both, then you have to make some decisions. Can you live with the setup violation, as long as the hold is fixed? Most designers go this way (better to waive a few setups and have all the holds fixed, rather than the other way around). Also, maybe the hold margin is too aggressive and could be backed off a bit to make things easier. If doing OCV, make sure CPPR is turned on.

- Kari
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Forums > Digital IC > Floorplanning, Place and route > timing critical design


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