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Forums > Digital IC > Floorplanning, Place and route

Subject: Physical Pin Minarea violation
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suresh235
Posts: 9
Online: User is Offline
2/11/2008 8:39 AM  
Dear all

wen i go for the command verifygeomertry after cts and just before routing using nanoroute. I get lots of violations for min area. When i check this in violation browser most of them are physical pin  min area violation. I generated the .io file using the encounter at floorplan stage and i dont have any fixed .io file. So can some one please tell me how could i over come this violations.

Thanks for ur help in advance

Suresh
abhiroy03
Posts: 7
Online: User is Offline
2/11/2008 8:10 PM  
Normally verify geometry/verify connectivity should be done after completing routing.If you are seeing minarea violations at physical pins even after routing,you should increase the size of the physical pins.(provided you haven't fixed the pins).This will get rid of the violations you are facing
suresh235
Posts: 9
Online: User is Offline
2/12/2008 12:41 AM  
hi

Thanks for your reply . but as rule for nanometer, its mentioned in the manual to verify the connectivity and geometry even b4 u start routing so that the violations can be fixed for a smooth routing. and i had done accordingly, but there are many pins with violations infact 95 % of the violations r physical pin viol.
Any advices

Suresh
sreeb
Posts: 6
Online: User is Offline
2/13/2008 10:33 PM  
I think you should always verify geometry before routing. No reason to route if you have a problem with your power plan. I'm a little surprised that you have any min area violations that aren't phisical pins. I just run verifyGeometry with -minArea option so they are ignored before routing.
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Forums > Digital IC > Floorplanning, Place and route > Physical Pin Minarea violation


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