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Forums > Digital IC > Floorplanning, Place and route

Subject: The clock propagating delay to the capture ff clk pin
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Tongju
Posts: 13
Online: User is Offline
4/07/2008 8:44 PM  
When I looked into FE timing report after clock tree build, I am expecting the actual clock propagating delay will be used in the setup timing check report.  I did see the actual clock propagating delay to the launch ff clock pin (from clock root through all the buffers/inverters) is used, but for the capture ff, the data required time is simply calculated by: Phase Shift - setup.  For examle, for the timing arc ff-->ff, if the clock cycle is 10ns, capture ff setup time is 0.1ns, then, FE simply told me the required time = 10 - 0.1 = 9.9ns.  Why is the clock delay to the capture ff clock pin (required time)  not calculated by actual clock path propagating delay while the clock path to the launch ff clock pin  did? Did I do something wrong?

Thanks,

Tongju
BobD
Posts: 80
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4/29/2008 7:40 AM  
Hi Tongju,

It sounds like something has malfunctioned in the process of switching the design from ideal clock mode to propagated clock mode, and peculiarly it has affected only the capturing clock in your case. I would first look to check whether different clocks driving the launch and capture- they probably are different. If they are different then I would examine the postCTS SDCs you're using and look at the "set_propagated_clock" SDCs that are present. The way clocks are propagated in Encounter is that for each AutoCTSRootPin in your clock tree spec file, a set_propagated_clock statement is appended to your SDCs. If this has malfunctioned for some reason, you'd see it reflected as a missing set_propagated_clock in your postCTS SDCs. Sometimes, users choose to manage clock propagation themselves and insert "set_propagated_clocks [all_clocks]" either interactively or as part of their postCTS SDCs. You may want to try that to see if you can cause the capture clock to be propagated.

Hope this helps,
Bob
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Forums > Digital IC > Floorplanning, Place and route > The clock propagating delay to the capture ff clk pin


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