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eminemshow
Posts: 71
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5/15/2008 10:41 PM
All, I need good idea when making CTS of clock gating structures. Due to some reasons, my clock tree has Latch & AND gate structures. And I can not change this to ICG. The terrible thing is that, I have to balance the Latch CK pin and AND A1 pin clock latency. How can I do this in SOC-E. I have tried several methods, but all failed. Waiting for your solutions.

bougantp
Posts: 18
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5/16/2008 1:16 AM
Hi, there is new functionality coming with 7.1usr2, and one of them is exactly what you are asking for: In CTS we have the possibility to defined dynamic macro model where in fact you define the pin where you want apply the shift, but you do not specify a value like standard macro model, you define a ref pin. This pin must be define as a through pin. Dynamically, CTS will balance the pin defined in your dynamic macro model with the attached ref pin. In your case you have to define a dynamic macro model on the CK pin of your latch, and the reference pin is the A1 pin of your AND. 71usr2 will get out soon.... In the meantime, what you can do, is to 1st run CTS, where you defined the root clock to your AND output pin, 2nd characterise the latency, 3rd run a new CTS on the wall clock, defining a macromodel on you Latch CK pin with the value equivalent of what you just characterize. It is not very fun, especially if you have many structure like this.... But I guess you can script it. Pat.

eminemshow
Posts: 71
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5/16/2008 10:57 PM
Posted By bougantp on 5/16/2008 1:16 AM Hi, there is new functionality coming with 7.1usr2, and one of them is exactly what you are asking for: In CTS we have the possibility to defined dynamic macro model where in fact you define the pin where you want apply the shift, but you do not specify a value like standard macro model, you define a ref pin. This pin must be define as a through pin. Dynamically, CTS will balance the pin defined in your dynamic macro model with the attached ref pin. In your case you have to define a dynamic macro model on the CK pin of your latch, and the reference pin is the A1 pin of your AND. 71usr2 will get out soon.... In the meantime, what you can do, is to 1st run CTS, where you defined the root clock to your AND output pin, 2nd characterise the latency, 3rd run a new CTS on the wall clock, defining a macromodel on you Latch CK pin with the value equivalent of what you just characterize. It is not very fun, especially if you have many structure like this.... But I guess you can script it. Pat. Bougan: I think the feature in 7.1 is the best solution, for your advice, I think it is really the best workaround. It is a tough job when I have several levels of clock gating structure....hoho. BRs

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Forums > Digital IC > Floorplanning, Place and route > All, I need good idea when making CTS of clock gating structures.