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thanhtung
Posts: 2
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| 5/17/2008 12:34 AM |
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| I defined power pins and using respective power pading cells. But when I use these commands to connect cell power pin to PW ring and PW ring to VSS and VDD pins, just connections of PW ring and power cell pins were done, no connections between PW ring and VSS/VDD pin (See picture)
Somebody can answer me, thank in advance.
[quote]###
### first, declare vdd/gnd pin's for all std-cells
###
globalNetConnect vdd -type pgpin -pin {vdd } -inst * -module {}
globalNetConnect gnd -type pgpin -pin {gnd } -inst * -module {}
### declare 0/1 vhdl/verilog constants to be on vdd/gnd supplys
globalNetConnect vdd -type tiehi -module {}
globalNetConnect gnd -type tielo -module {}
###
### IO pads
### - All the instance names for the IO pads must have the "io_" prefix
###
globalNetConnect vdd -type pgpin -pin {vdd } -inst io* -module {} -override
globalNetConnect gnd -type pgpin -pin {gnd } -inst io* -module {} -override [/quote]
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Kari
Posts: 60
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| 5/23/2008 1:57 PM |
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Hi,
I'm not really clear on your question. If you mean you don't see actual routes between the pwr/gnd IO pads and the pwr/gnd ring, then that's because globalNetConnect doesn't actually route the wires. (It just assigns the connectivity.) You need to use Route->Special Route and use the Pad Pins option. Is that your question?
- Kari |
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thanhtung
Posts: 2
Online:
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| 5/25/2008 2:32 PM |
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Hi, I have already corrected this error. Problem did not come from globalNetConnect command, there is a error in LEF file in property descriptions of power padding.
Anyway thank for your help. |
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