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Subject: how could FE extract coupled C when doing timeDesign?
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yhu
Posts: 10
Online: User is Offline
6/02/2008 8:47 PM  
Hi,All based a routed design,when i do timeDesign,FE extracts RC,below is a part of the log: Nr. Extracted Resistors : 1721541 Nr. Extracted Ground Cap. : 1821440 Nr. Extracted Coupling Cap. : 0 actually,it's not what I expected,i wanna coupling cap be expected. i try to setExtractRCMode -coupled true,it does not work,and after doing timeDesign,the -coupled is false when getExtractRCMode.. so ,could anyone help,thanks in advance.
Devi
Posts: 6
Online: User is Offline
6/02/2008 10:29 PM  
To extract coupled cap. during time deisgn, You need to enable -si option of timeDesign.
Devi
Posts: 6
Online: User is Offline
6/02/2008 10:29 PM  
To extract coupled cap. during time design, You need to enable -si option of timeDesign.
yhu
Posts: 10
Online: User is Offline
6/04/2008 2:34 AM  
Devi,
Thanks a lot.
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Forums > Digital IC > Floorplanning, Place and route > how could FE extract coupled C when doing timeDesign?


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