Thursday, January 08, 2009     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Digital IC > Floorplanning, Place and route

Subject: LVS after place&route may fail due to clock tree buffers
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
Naderi
Posts: 33
Online: User is Offline
6/16/2008 5:36 PM  
Hello All

An LVS after place&route should compare final layout with input verilog code (i mean that verilog code used as input for place&route tool).

But during place&route, some new buffers may be added  automatically by the tool which were not in the original verilog code.

My question is how LVS should realize the new buffers?
when I run LVS by Calibre, it fails with many error messages like this:

Error: No matching ".SUBCKT" statement for "BFLVTX1" at line 1490 in file "/tmp/lvsRunDir/_decoder36.v.sp"

BFLVTX1 is a buffer used from std library.

Can anyone help me please with this issue?

Thanks,
Ali Naderi
Kari
Posts: 81
Online: User is Offline
6/16/2008 5:46 PM  
Hi Ali,

LVS is not meant to compare the STARTING verilog to the final layout. It is meant to compare the FINAL verilog netlist to the final layout. All the buffers in the final layout will also be in the final netlist.

- Kari
Naderi
Posts: 33
Online: User is Offline
6/17/2008 7:01 AM  
Hi Kari,

Thanks for you reply.
Then how do you make sure your final layout is functioning exactly like the original verilog code?
Full simulation of final netlist (post-layout) may not be possible as digital designs are usually very large in my case 4M gates. Such simulation time is more than few months.
In analog, we used compare layout with schematic and the schematic may play a roll like starting verilog codes.

Regards,
Ali
Kari
Posts: 81
Online: User is Offline
6/17/2008 9:06 AM  
Ali,

To compare your starting verilog to your final verilog and make sure the functionality has not changed, you need to run Conformal LEC. You can also compare the starting RTL to the final verilog. LEC does not verify layout, but if you use LEC to make sure the final netlist is functionally equivalent to the starting netlist and then use LVS to make sure the layout matches the final netlist, you should be good.

- Kari
Naderi
Posts: 33
Online: User is Offline
6/17/2008 9:31 AM  
Okay, the LEC is what I need to learn.
Thanks again,
Ali
Posting to forums is available to community members only.
Login or Register
Forums > Digital IC > Floorplanning, Place and route > LVS after place&route may fail due to clock tree buffers


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.