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sreilly
Posts: 6
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6/18/2008 9:02 AM
Hi there, can anyone tell me how to make Encounter place pins on restricted layers, for example on metals 1 & 2 only. Ultimately i'd like my pins placed on a given boundary edge & in a pre-determined order. Thanks Stu p.s I'm actually an alaog layout guy using Encounter (for the first time) to place and route a large digital block in an analog chip. Apologies for the simple Q's, there will be more.

BobD
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6/18/2008 10:08 AM
Hi Stu, Welcome to the forums! You may want to use First Encounter's Pin Editor (Edit->Pin Editor) to accomplish this task. It allows you to preassign pins on certain layers, in user-defined order, and on certain sides. If you're looking for more of a way to constrain the location of pins which automatic pin placement will honor, there are constructs available for that as well (pin groups, pin guides, pin constraints, etc). Maybe you could have a look at the Pin Editor and post back if that was the kind of thing you were looking for and we can go from there. Hope this helps, Bob

sreilly
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6/19/2008 4:01 AM
Hi Bob, thanks for your reply. I seem to be getting somewhere and i followed through the manual regards pin editor. I can now sort of re-position and re-order pins. Now i suppose that if you give pins no placement constraints that First Encounter will place each pin in what it deems to be the most sensible position? My next question having done this, can i tell First Encounter that moving pins for easier route access (on a specified grid) is ok as long as it maintains my specified order? Again i will continue to go through the manual but any advice i can get is appreciated. Thanks Stu

BobD
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6/19/2008 8:01 AM
Yes, without any constraints when placeDesign runs it places the IO pins such that they are as close as possible to the instance(s) each pin is connected to. I like to visually assess this using "selectIOPin *"- if the tool has done a good job, you should see straight flight lines connecting from each IO pin to the nearest instance each is connected to. From there, you can constraint pin placement in several ways. There's a pretty good write up on this subject in the SoC-Encounter User's Guide, described in most depth in the Partitioning section under the "Assigning Pins" section. It's worth noting explictly that the constraints available for partition pins also apply to IO pins (the general convention is that the -cell option should be used with the top cell name specified as the cell). If you're you're unsure what the top cell name is you can use "dbGet top.name". Dropping down a level in detail to your specific request of "Can FE place IO pins along a given edge, maintaining the order while optimizing the pin location for easier route access?". I've worked through this scenario in the past with mixed results honestly. Perhaps if I describe the mechanisms used to constrain the tool to do what you're asking for you could try it on your design to see if it aligns with your needs? createPinGroup myGroup -cell testcase -pin {out1 out2} ->order is important here ->do not specify -optimizeOrder if you want the order maintained as specified createPinGuide -edge 1 -pinGroup myGroup -cell testcase -layer {2 3} ->Edges start at "0" with the lower left corner and increases by 1 for each edge clockwise ->Visually, in the floorplan view after createPinGuide you should see small white guides around the edges after this step ->By default, the system disallows pins on M1. If you require M1 pins, please post back for further guidance. From there, you should be able to "placeDesign" and have the tool place the standard cells and IO pins. I should mention that I've seen some quality of results issues while attempting to constrain the tool in this specific manner (order maintained while giving the tool flexibility to determine locations). Pin assignment with groups and guides sometimes likes to stack up the pins at the user-defined minimum spacing rather than truly optimizing their locations when the order is required to be maintained. Sometimes, it is easier to write a script using "editPin" to place the pins in the order you like with a user-determined gap between each pin. editPin is smart enough to dodge around power preroutes and such so I thought I'd mention that as an alternative. Great questions- keep 'em coming! Hope this helps, Bob

sreilly
Posts: 6
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6/23/2008 6:57 AM
Hi Bob, agian thanks for your info. I'd just typed a long winded reply and lost connection before i got to post it, very annoying!!! Anyway the short reply was that i need to try a few test cases of constraining the pin placement and compare it no constraint placement. My gut feeling is that its more efficient to let the tool place the pins and then i can deal with the connection at the level above, given that its an analog chip and i'll be custom routing at top-level anyway. Do you mind another couple of Q's? (should i start another thread for these, i don't want to clog up the forum) 1) How do you tell FE (First Encounter) that its ok to stack vias and contacts, it appears not to be at present? 2) Can i get FE to indicate what % of area of my floorplan is being utilised once i've placed my logic? At present i'm setting my floorplan dimensions BEFORE i place the logic. Is this standard practice as this assume i have reasonable feel for the block size before i place any blocks or do any hook-up? Cheers Stu

BobD
Posts: 80
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6/23/2008 7:56 AM
Hi Stu, You're welcome. 1) For via stacking, the tool should determine this automatically from rules present in the technology LEF. Either your technology LEF is a crude one (and lacks the details to enable the tool to stack vias) or there's something going wrong. It may also depend on whether you're talking about signal routes or power routes in terms of the needed action on your part to encourage stacking. Maybe you could provide some additional detail on your scenario? 2) For density you probably want to use a command like "queryPlaceDensity" to assess what the standard cell density is after floorplanning the design. This TCL command is equivalent to clicking the circular green icon with a percent sign on the main FE GUI. The difference between queryPlaceDensity and the density # you target when initializing the floorplan size is that nuances like placement blockages, power preroutes that preclude standard cell placement, placement density screens and the like aren't taken into account when determining the initial size of the design as a percentage. It's probably best to post new topics individually so that people can see if there's a subject line they're interested in, but no biggie. Either way. Thanks, Bob

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Forums > Digital IC > Floorplanning, Place and route > First Encounter pin placement/layer

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