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Forums > Digital IC > Floorplanning, Place and route

Subject: Is it a MUST to use capTable to do .13um design?
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pico
Posts: 8
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6/23/2008 2:03 AM  

If there is no capTable available, fe will use WLM?


Thanks.
BobD
Posts: 80
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6/23/2008 7:42 AM  
First off, welcome to the forums! Thanks for your post.

No, cap tables are *not* a MUST. If there is no cap table available, FE will *not* use a wireload model. It will derive parasitics from actual route topologies using approximations made from whatever information is available in the technology section of your LEF file to determine resistances and capacitances.

Whether this is sufficient to accurately model your 0.13 process depends on whether you're using FE as a prototyping tool -or- as an implementation tool. If prototyping, it may very well be sufficient. If implementation probably not.

In general, it is always best to run with a cap table, but situations do arise where they're not available yet and we want work to proceed. Cap tables can be created using the FE command "generateCapTbl". The command takes an ICT file as input (which describes the process stack information, which usually comes from your process provider) and produces a cap table. Just thought I'd mention those details in case it wasn't clear in general where this information should come from.

Hope this helps,
Bob
pico
Posts: 8
Online: User is Offline
6/23/2008 7:38 PM  
Thanks Bob for your detailed information.
pico
Posts: 8
Online: User is Offline
6/24/2008 6:58 AM  
Is there any utility to convert SNPS itf to ict file format?
I think these two describle the same thing.
BobD
Posts: 80
Online: User is Offline
6/24/2008 7:05 AM  
Hi pico,

Would it be possible for you contact your local Cadence AE, or open a service request with http://sourcelink.cadence.com with this request?

Thanks,
Bob
pico
Posts: 8
Online: User is Offline
6/24/2008 8:54 AM  
Bob,
I'll have a try.
Thank you.
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Forums > Digital IC > Floorplanning, Place and route > Is it a MUST to use capTable to do .13um design?


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