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Posting to forums is available to community members only. Login or Register |
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davidbd
Posts: 4
Online: 
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| 7/15/2008 2:52 AM |
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Hi,
I am trying to plan my chip power grid and I would like to know if you have any guidelines for the following :
In
/general I need to know how to :
- Calculate the
correct core ring width
- Calculate the
correct power strips width
- Calculate the
correct number power strips
Synthesis Power Plan but I think the results are not reasonable and produce many DRC violations need to be fixed by hand.
I thought using the addRing and addStripe commands instead of the above automatic flow but I need to know the correct parameter for this commands.
What is the correct/working flow ?
Any help will be appreciated.
David.
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Kari
Posts: 81
Online:
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| 7/15/2008 2:54 PM |
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Hi David,
addRing and addStripe are the right commands to use (along with sroute for IO connections, block connections, std cell rails, etc.) Coming up with the widths and spacings to use is a question asked pretty often. It depends on your technology, available metal layers, power consumption, etc. Sometimes people come up with a spreadsheet that calculates the total metal width needed based on the desired IR drop. If your design is a flip-chip, the calculations are not so easy. (But you need less grid, which is nice.) If you have a previous design you can base your grid on, that always helps. The best thing is to do an IR-drop analysis as early as possible so that you can make changes if it looks bad. I know this is not much help, but hopefully it will give you some ideas. You could also put in as much power as you can and still be able to route. The layers will end up getting metal fill anyway, so you might as well use the area for your pwr/gnd grid, right? :-)
- Kari |
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davidbd
Posts: 4
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| 7/15/2008 11:51 PM |
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Hi Kari,
Thanks for the help but I still wanted to know hot to calculate those parameters:
- Core ring width
- Stripe width and number
How the Encounter Power Synthesis tool is calculating those numbers ?
I am getting some trial resoults and I would like to review them, Is there any rule of thumb for this parameters ?
David |
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eminemshow
Posts: 75
Online:
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| 7/16/2008 4:17 AM |
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Posted By Kari on 7/15/2008 2:54 PM
Hi David,
addRing and addStripe are the right commands to use (along with sroute for IO connections, block connections, std cell rails, etc.) Coming up with the widths and spacings to use is a question asked pretty often. It depends on your technology, available metal layers, power consumption, etc. Sometimes people come up with a spreadsheet that calculates the total metal width needed based on the desired IR drop. If your design is a flip-chip, the calculations are not so easy. (But you need less grid, which is nice.) If you have a previous design you can base your grid on, that always helps. The best thing is to do an IR-drop analysis as early as possible so that you can make changes if it looks bad. I know this is not much help, but hopefully it will give you some ideas. You could also put in as much power as you can and still be able to route. The layers will end up getting metal fill anyway, so you might as well use the area for your pwr/gnd grid, right? :-)
- Kari
Good comments, Kari |
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davidbd
Posts: 4
Online:
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| 7/16/2008 5:22 AM |
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Hi Kari,
You sent same answer
David.
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Kari
Posts: 81
Online:
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| 7/16/2008 8:16 AM |
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Hi David,
Actually eminemshow quoted my reply in his comment. :-) I don't have any insight into how Synthesize Power Plan calculates its numbers. Can you tell me what technology your design is, how many metal layers, the main frequency, and whether or not it's a flip chip? I can't promise anything, but if it's similar to one of my designs, maybe I can give you some general numbers to start with.
- Kari |
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davidbd
Posts: 4
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| 7/16/2008 8:22 AM |
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Hi Kari,
Thanks a lot for the help, sorry I saw the comments.
My design detailed:
- TSMC65nm GP
- 6LM
- 2000mw total power
- No flip chip
David
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Kari
Posts: 81
Online:
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| 7/16/2008 9:30 AM |
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Hi David,
The closest I can get is a 10-layer flip chip. Layer 10 is the RDL. The stripes are on layers 4 - 9 (with m1 being the std cell rails of course). Stripe widths here are 1.5 for m4 -m7, and 7.5 for m8 - m9. The distance between VDD/VSS stripe sets is about 22 um. It is typical to use the top 2 layers of a design for mostly power, if you have enough routing resources on the other layers. Also, a lot of times the top 2 layers of a design are thick. So we have a total width here of 21 um (not added across the whole chip, just one set of stripes). If you were also doing flip chip, you could have a total width of 21 um spread across your 6 layers (again just one set of stripes, to be duplicated over the whole chip). HOWEVER, you are not doing flip chip, so you will need more power than what we have here. How much more? That I can't really say. You could start by doubling this and see if you can still route. If you can, then get to that early IR drop analysis and make sure things look good. Does that make sense? Let me know if I should explain more. :-) Hope this helps, and remember these are just LOOSE GUIDELINES. The proof is in the IR-drop analysis!
- Kari |
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290702500
Posts: 1
Online:
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| 7/16/2008 10:53 PM |
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Posted By Kari on 7/16/2008 9:30 AM
Hi David,
The closest I can get is a 10-layer flip chip. Layer 10 is the RDL. The stripes are on layers 4 - 9 (with m1 being the std cell rails of course). Stripe widths here are 1.5 for m4 -m7, and 7.5 for m8 - m9. The distance between VDD/VSS stripe sets is about 22 um. It is typical to use the top 2 layers of a design for mostly power, if you have enough routing resources on the other layers. Also, a lot of times the top 2 layers of a design are thick. So we have a total width here of 21 um (not added across the whole chip, just one set of stripes). If you were also doing flip chip, you could have a total width of 21 um spread across your 6 layers (again just one set of stripes, to be duplicated over the whole chip). HOWEVER, you are not doing flip chip, so you will need more power than what we have here. How much more? That I can't really say. You could start by doubling this and see if you can still route. If you can, then get to that early IR drop analysis and make sure things look good. Does that make sense? Let me know if I should explain more. :-) Hope this helps, and remember these are just LOOSE GUIDELINES. The proof is in the IR-drop analysis!
- Kari good boy!!
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Kari
Posts: 81
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| 7/17/2008 7:17 AM |
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Thanks, but I'm a girl. :-)
- Kari |
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eminemshow
Posts: 75
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| 7/20/2008 3:31 AM |
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Posted By Kari on 7/17/2008 7:17 AM
Thanks, but I'm a girl. :-)
- Kari
Kari，you are from Cadence？
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Kari
Posts: 81
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| 7/21/2008 6:55 AM |
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Yes, I work at Cadence. :-)
- Kari |
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aidans
Posts: 35
Online:
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| 7/21/2008 7:29 PM |
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HI Kari
"Stripe widths here are 1.5 for m4 -m7, and 7.5 for m8 - m9. The distance between VDD/VSS stripe sets is about 22 um."
I don't fully understand the distance of 22 um?
Which scenario is right, A or B?
scenario A
|7.5umVDD|<----------22um--------------------->|7.5umVSS|<----------22um------------|7.5umVDD|
scenario B
|7.5umVDD| |7.5umVSS|<----------22um--------------------->
|7.5umVDD| |7.5umVSS|
Aidans
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aidans
Posts: 35
Online:
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| 7/21/2008 7:29 PM |
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HI Kari
"Stripe widths here are 1.5 for m4 -m7, and 7.5 for m8 - m9. The distance between VDD/VSS stripe sets is about 22 um."
I don't fully understand the distance of 22 um?
Which scenario is right, A or B?
scenario A
|7.5umVDD|<----------22um--------------------->|7.5umVSS|<----------22um------------|7.5umVDD|
scenario B
|7.5umVDD| |7.5umVSS|<----------22um--------------------->
|7.5umVDD| |7.5umVSS|
Aidans
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Kari
Posts: 81
Online:
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| 7/22/2008 7:27 AM |
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Hi Aidans,
Scenario B is what I meant. If you don't want VDD and VSS stripes together, then you can use something like Scenario A but with 11 um spacing. The idea is that between any 2 VDD stripes there is 22um space, and between any 2 VSS there is 22um space.
- Kari |
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aidans
Posts: 35
Online:
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| 7/22/2008 8:06 PM |
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Thank you Kari
I push this question step further:
Fro IR drop and leakage point of view, which senario is better, B or C?
Senario B
|7.5umVDD| |7.5umVSS|<----------22um--------------------->
|7.5umVDD| |7.5umVSS|
Senario C
|7.5umVDD| <----11um-------> |7.5umVSS|<----11um-------> |7.5umVDD| <----11um-
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Kari
Posts: 81
Online:
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| 7/23/2008 6:33 AM |
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I don't think it matters. You have 22um between VDD stripes in both cases, and 22um between VSS stripes in both cases. So IR drop is not affected. Leakage is more a function of the cell library than the power stripes.
- Kari |
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