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Forums > Digital IC > Floorplanning, Place and route

Subject: about the error of "checkDesign -all"
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sbssdh
Posts: 6
Online: User is Offline
7/20/2008 12:29 AM  
hi:

who can tell the cause of the following the error in the command "checkDesign -all"


**ERROR: Input netlist has a cell PANA1AP which is marked dont_use in the library.
**ERROR: Input netlist has a cell PX2 which is marked dont_use in the library.
**ERROR: Input netlist has a cell PI which is marked dont_use in the library.
**ERROR: Input netlist has a cell PO2 which is marked dont_use in the library.
**ERROR: Input netlist has a cell PO16 which is marked dont_use in the library.


3ks
Black Lutin
Posts: 11
Online: User is Offline
7/21/2008 1:04 AM  
Hi,

Generally, it is not a real problem. I suppose, according the names, these masters to be pads or macros. You have certainly a dont_use in your .lib file for these masters.
An other case is that the dont_use for the syntesis are not teh same than the dont_use for the encounter flow.
The last case is when during synthesis, people add master manually (by vhdl, or by editing the netlist). An with this method you cab add dont_use masters.

Regards ...
sbssdh
Posts: 6
Online: User is Offline
7/21/2008 1:56 AM  
hi:
   yes, these masters are pads, but they are the type that used by the IO  instance.
and when i synthesis, these masters are not set the "dont_use" attribute. 
   so  why  encounter report these errors?

  3ks
Black Lutin
Posts: 11
Online: User is Offline
7/21/2008 2:43 AM  
Hi,

Are you using the same .lib files under encounter and your synthesis tool ?
Perhaps also that encounter puts automatically a dont_use attribute on all pad masters. You can check this after having read your lib and LEF files with dbCommand.

Regards ....
Kari
Posts: 81
Online: User is Offline
7/21/2008 6:54 AM  
Hi 3ks,

Encounter is just warning you that you have a dont_use attribute on these cells in your .lib files, but they appear in the netlist. Since they are IO Pads, you can ignore this and continue with your flow (unless there is some reason those IO cells should not be used). It's always good to check these warnings though. Let's say you didn't want to use any buffers higher than 16x, so you had a dont_use on BUF24X and BUF32X, but the starting netlist contained some BUF24X cells. Then you would want to see this warning, so that you could swap those buffers out for lower drive buffers.

- Kari
sbssdh
Posts: 6
Online: User is Offline
7/22/2008 10:43 PM  

hi:
   i have solved these errors . this just because i set the IO's operation condition in VP script, but i
don't set the operation condition in implementation script. now i set the same operation conditon, these warning disappear.

  3ks
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Forums > Digital IC > Floorplanning, Place and route > about the error of "checkDesign -all"


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