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Forums > Digital IC > Floorplanning, Place and route

Subject: power planning for 3Metal Layer process
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kulprashant
Posts: 2
Online: User is Offline
7/20/2008 9:09 PM  
Hi,

I am working on the AMS design and i will be working on the P&R flow for digital block.
this is 3 Metal layer process design with the 0.35u Technology.
please let me know how to do the power planning for perticular design beacuse it 3 lm process and which metal layer goes for the power routing (specially how to design the core rings & straps) and signal. I wnt through the user guide fo SoC Encounter, nothing has given for 3 LM process)
it would gr8 help if some one assist me ASAP.

Thanks & Regards,
KulPrashant
Kari
Posts: 81
Online: User is Offline
7/24/2008 1:30 PM  
Hi KulPrashant,

I guess you would do the rings and stripes in m2 and m3, the std cell rails in m1 (assuming your std cell pwr/gnd pins are in m1), and you'll have to adjust the widths and spacings to make sure you have enough routing resources for the signal routes. Be sure to run IR-drop analysis to make sure you have enough power. Sorry I can't be any more specific, you probably already knew all of this. :-)

- Kari
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Forums > Digital IC > Floorplanning, Place and route > power planning for 3Metal Layer process


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