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PavleM
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11/15/2007 2:46 PM
Hello all, I have a couple of newbie questions on the suggested design flow of the evaluation PCB for my chip design. I've done my chip design in Cadence Virtuoso, and sent it to the manufacturing house for tapeout and packaging. Now I would like to design a PCB for it in Cadence Allegro, and if possible simulate the whole IC-package-PCB system before manufacturing the PCB. Packaging will be done for me, so far I can only get the physical characteristics of the package (type, dimensions, pin pitch etc), and I'm not sure that I will be able to obtain the details on how wire bonding was done. Therefore, I was thinking of exporting my IC data from Virtuoso, placing it inside a package I'd generate with Package Wizard, and doing simple autorouting. 1. For purposes of creating the package, how do I get my physical IC data into Allegro? Can I import it into the Package Designer, or do I need to go through Design Entry CIS, and which format to use? 2. For simulating the whole IC-package-PCB, can I use the netlist extracted by Mentor Graphics Calibre (includes all the parasitics)? What format should I extract the data into - HSPICE, Spectre or some other? What component of Allegro do I use for simulating (in Virtuoso I was using Analog Environment with Spectre or HSPICE models)? Sorry for the long post - if there's some sort of a tutorial covering this flow, I'd appreciate info on where to find it. Thanks a lot in advance! Pavle University of Illinois

PavleM
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12/06/2007 1:56 PM
Hi all, Given that Cadence takes great pride in being able to cover all the chip design phases, I find it strange that I got no replies on how to use my Virtuoso design in Allegro. I would really appreciate at least a pointer on where to start - what initial Allegro tool to use (I suspect Capture CIS), and what format to use to export my chip data from Virtuoso? Regards, Pavle

dbaldwin
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12/06/2007 3:01 PM
The Allegro RFSIP product has the functionality to generate a die footprint and the die text file used in Packaging. Depending upon the type of IC (digital, Analog or Mixed) and data speeds would dictate the method of simulation and products used. Your comments about the packaging being taken care of and not being much of a factor is in my opinion far from reality. Packaging is just as important as the PCB and more so in terms of budgeting. Mainstream design flows comprehend co-design of the IC-PKG-PCB. Allegro has this functionality as well. Best Regards, Dan

PavleM
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12/07/2007 11:16 AM
Dan, thanks a lot for your reply. Perhaps I wasn't clear on package issues, I agree that it's extremely important. However, since I have no control over how it will be performed, and since my chip has low-speed inputs and outputs (~15 MHz), I feel modeling the package parasitics using several lumped elements with vendor-provided values should be sufficient (and the only possible option, given the lack of detailed packaging data). Back to my original issue, my IC is a mixed-signal low speed chip. I have the LQFP package footprint files I can use in PCB Editor. Now I need to relate this package to the Virtuso-designed IC inside it - what tool would you suggest for this purpose? I am currently attempting to create a new part in Design Entry CIS. I can set "PCB Footprint" property of the part to match the package footprint I have, but the only reasonable "Implementation Type" offered is "PSPICE Model". Now, I can extract my layout from Virtuoso using Mentor Graphics Calibre PEX (outputs HSPICE, Spectre, etc) or Assura RCX (outputs SPICE, Spectre, etc). Would Assura's SPICE output be the one to use as "Implementation" for the part? Or perhaps this method is completely off the mark - I would appreciate any suggestions.

BillAcito
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1/09/2008 11:28 AM
I checked with one of our VLE/APD design experts, and he suggested the following: Tools Needed: Composer (Create IC or SiP designs), VLE (IC layout), SiP Layout and ADE (Virtuoso Analog Design Environment): Glue of IC and SiP tools available using SiP RF Architect 1. Export the DIE from VLE that creates a Composer symbol and SiP footprint for Allegro Package Design tool 2. Use above generated SiP symbol (Composer) and footprint (SiP layout) in SiP design 3. Add package to the die(s) in SiP Layout and extract parasitics using solvers. 4. Back-annotate this extracted model (and critical Package routes) back to SiP design schematic (Composer) 5. Use ADE to simulate Composer SiP design together with IC DIE and Package parasitics -- ADE is Composer integrated with Spectre and other simulators. - Calibre extracted IC parasitics would be simulatable in ADE 6. Capabilities like design of off-chip components, partial circuit extraction for simulation, MTS would augment the solution He also suggested that you take a look at the SiP RF webinars that were offered starting in September of last year, and will go on through April: http://www.cadence.com/webinars/webinars.aspx?xml=circuit_simulation_webinar_series Regards, Bill

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