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Subject: Estimated power consumption of a full custom digital IC design
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spbalan04
Posts: 2
Online: User is Offline
4/25/2008 7:53 AM  
I have drawn a full custom digital circuit using Cadence Virtuoso and have simulated it using Spectre. I wish to obtain the dynamic (including both switching and short-circuit) and leakage power components of the circuit. How do I estimate it for a given set of input stimuli. I also like to know as to how do I get to know the worst case delay of the circuit, for rising and falling transitions separately? Expecting your clear replies as I am quite new to full custom digital IC design.

Thanks,
Bala
lukelang
Posts: 18
Online: User is Offline
4/30/2008 12:49 AM  
Bala,

Your question is broad and covers a series of tools. A lot more detail is needed to properly answer your question. In general, the flow can be split into the following parts:

1. Extraction (QRC)
2. Simulation (Sprectre, Ultrasim)
3. Analysis (VoltageStore - IR/EM analysis)
4. Litho effect on manufacturability and timing, if 65 nm or below.

The best way to obtain support is to file a Service Request with Cadence or talk to your Cadence Account Executive. The solution that you are looking for cannot be adequately addressed in this forum.

Luke Lang
spbalan04
Posts: 2
Online: User is Offline
4/30/2008 4:58 AM  
After drawing the transistor level schematic using Cadence Virtuoso and subsequent simulation using Spectre, I was able to see the current waveform. When I used Wavescan on the netlist (transistor level SPICE like netlist), I was able to see the power consumption in microWatts. But there were two power values. One, I think corresponds to the current flow when the circuit turned ON multiplied by the supply voltage. I think this might be the dynamic power component. Apart from this, there was another power component. I don't know whether this refers to the total power consumption as it was higher than the dynamic component. Could you kindly clarify? I haven't extracted the layout and the above figures are obtained before getting the layout.

Thanks,
Bala
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Forums > Special Topics > Low power > Estimated power consumption of a full custom digital IC design


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