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Subject: some different questions
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buenos
Posts: 14
Online: User is Offline
12/16/2007 12:41 PM  

hi

I am/was a Protel user, but now, I am changing to Allegro. I have read 1000-2000 pages of manuals, but I still have questions: 

1.-how to manually route a group of signals together? or a bus? if its possible.

2.-what is thieving?

3.-is there a list about the DRC error codes?

4.-whats are those lots of classes/subclasses, and what are they used for usually? (these mean around 100 layers. in Protel, I used around 20 layers max, including silk, mechanical...)
psj
Posts: 34
Online: User is Offline
12/17/2007 12:38 AM  
1-how to manually route a group of signals together? or a bus? if its possible.

Atleast in the 15.2 version it is not possibe ....


2.-what is thieving?



3.-is there a list about the DRC error codes?

Yes , it is explained in the manuals in detail about all DRC errors. Even if you click on the menu button " i " , i.e show element and then click on the DRC error, the information is displayed as what DRC error has occured .....



4.-whats are those lots of classes/subclasses, and what are they used for usually? (these mean around 100 layers. in Protel, I used around 20 layers max, including silk, mechanical...)


Yes , there are lots of classes and subclasses .....But it totally depends on the individual ( as per the requirement)....whichever classes are to be used and which are not to be used.....it is not neccessary to use or define alll classes....

Regards,
Prajakta.
kp
Posts: 53
Online: User is Offline
12/17/2007 2:08 AM  
You can route a bus of signals by selecting as a temp group or dragging a box over the cline ends, vias or pins.

KP
kp
Posts: 53
Online: User is Offline
12/17/2007 2:23 AM  
Thieving is the process of balancing the amount of copper on both sides so that the plating is as even as possible. Typically the board fabricator would add this around the panel scrap edges but if the balance is poor they may request to put some also on the board. We disagree with the fabricator putting thieving on the board as they has no idea of the electrical requirements of the design. Instead of adding thieving, which is usually lots of floating copper pieces, we add copper pour areas and connect to ground.

KP
buenos
Posts: 14
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12/17/2007 3:50 AM  
thank you for the fast enswers.

which sub/classes are usually used, and for what? i think the etch, stackup is clear for me, but the geometry and manufacturing? just please give an example.
kp
Posts: 53
Online: User is Offline
12/17/2007 4:15 AM  
Only electrical items are in the stack-up and as such are very straight forward.

Board Geometry - is for Mechanical items, such as the Card Profile which would go on the Outline subclass. Extra pieces of silkscreen or soldermask that are card specific and obviously dependent on the side of the card. If you dimension up the card profile this could go on dimension. Other subclasses are auto-place/router specific such are Place_Grid, Rooms, Switch_areas etc. Constraint areas are used for locally restricted rule change areas.

Package geometry – Broadly the same as the board geometry but are component symbol specific items.

Component value, device type, tolerance and user part numbers are part specific values which you may wish to add to your components depending on your internal setup and possible extractions of data that you may require later on.

Drawing Format is mainly used for your drawing blanks etc for your assembly and drill drawings.

Manufacturing subclasses are used for post routing. Some such as NCDRILL’s are generated automatically by the manufacturing -> nc -> drill legend. Same goes for Autosilks. No probe’s are used to define tespoint keepout areas, no_gloss are used to restrict the automatic gloss routines.

Analysis – Used automatically by the analysis parts of the tool set.

Ref Des – Component references used for silks, drawings etc.

KP
buenos
Posts: 14
Online: User is Offline
12/17/2007 4:54 AM  
thanks.
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Forums > Silicon-package-board > PCB Design > some different questions


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