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Subject: Via on SMT pin DRC
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Author Messages
Vignesh
Posts: 0
Online: User is Offline
3/16/2005 1:01 AM  
Same net DRC off. How could we avoid that via on pin problem. Or how could we identify the DRC.
Padmin
Posts: 0
Online: User is Offline
3/16/2005 6:47 AM  
Under your Physical Rules, ""Set DRC modes..."" button, make sure ""Pad/Pad direct connect"" is set to ""Always"". Then under Physical Rules, ""Set values..."" button, make sure your ""Pad/pad direct connect"" is set to ""Not Allowed"". This will flag a DRC when the via is within the SMT padstack. If you have same net checking turned on, your via - pin spacing constraint will apply.

You may want to look at SourceLink solution 11165996 for more info. I hope this helps.
Vignesh
Posts: 0
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3/16/2005 10:05 PM  
No Its not Applicable to my query.
I have set the, Same Net DRC ""off"". If I route with a via on a SMT pin , it should show DRC. How can I achevie this.
Padmin
Posts: 0
Online: User is Offline
3/17/2005 6:02 AM  
Just to make sure... Please verify:

1)
Under your Physical Rules, ""Set DRC modes..."" button, you have ""Pad/Pad direct connect"" set to ""Always"" for the 'proper' constraint set?

2)
Under Physical Rules, ""Set values..."" button, you have ""Pad/pad direct connect"" set to ""Not Allowed"" for the 'proper' constraint set?

If so, it would probably be best to open a Service Request with Cadence Support to look at your design.
Vignesh
Posts: 0
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3/17/2005 5:37 PM  
Thanks I will get support from Cadence
Norm
Posts: 1
Online: User is Offline
5/01/2006 9:49 AM  
I have a similar issue. I have added my via so it is just about
tangent to the smt pad. It actually overlaps the smt pad by a
bit. Is there a way to have allegro not drc?
Boma
Posts: 10
Online: User is Offline
5/17/2006 11:41 AM  
If you are using 15.5.1 latest ISR, try going to Keyboard Commands and look for a command called "via_checks_report" and see if this will help identify your issues.
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Forums > Silicon-package-board > PCB Design > Via on SMT pin DRC


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