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Forums > Silicon-package-board > PCB Design

Subject: keepout question
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mihaii
Posts: 0
Online: User is Offline
5/09/2005 11:07 AM  
I want to create a bottom keepout area:
-no bottom component placement
- no vias
-no bottom etch

I've created a bottom keepout area:
when I place a through hole e-cap on the top I don't get any DRC error.

How can I get a DRC error when a through hole component is placed on the top?

Thanks,
nzdave
Posts: 0
Online: User is Offline
5/09/2005 1:02 PM  
You need to put bottom side place bound shapes on your symbol pads. Give them the maximum protrusion of your pins (2mm?)
mihaii
Posts: 0
Online: User is Offline
5/09/2005 2:34 PM  
This sounds complicated. Is there a easier answer to my problem?
I assumed Allegro to be smart and realize when a symbol has through hole components and give me a DRC error.
AshCan
Posts: 20
Online: User is Offline
5/22/2005 11:41 PM  
Defining PLACE_BOUND_TOP shapes in your package symbols is a standard part of good library development. Every through-hole part is also present on the second side of the PCB (where the leads protrude or are clinched perhaps). Therefore it is good library development practice to define PLACE_BOUND_BOTTOM shapes describing these areas where the leads are present. Incorporating this as part of your lib development process requires very little extra time and will address your immediate problem.
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Forums > Silicon-package-board > PCB Design > keepout question


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