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Subject: Issues with shorting nets together
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willbertsche
Posts: 4
Online: User is Offline
4/12/2008 1:29 AM  
Hi,

    I was trying to short nets together using the NET_SHORT property added to a custom netshort part (to short multiple nets together. I tried following the details from the following app note:
http://www.cadence.com/community/allegro/resources/resources_PCB/LR/appnote_net_short.pdf

    I tried following the solution in which one makes  a part with multiple pins that are shorted in allegro 16.01. It may be that I'm mis-interpreting the constrution of the part. I looks to me that there is a central pin (1) with a quite large via, and two other smaller pins (2,3) which are vias that are entirely contained withing the large central via.

    I tried making my own part as described, and it seems to short signals, but I get DRC errors for violations of line to thru-hole spacing. Is there some way to avoid this outcome, other than removing line/tru spacing constraints? Have I mis-interpreted the creationg of the short symbol?

Thanks,
Will Bertsche
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Forums > Silicon-package-board > PCB Design > Issues with shorting nets together


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