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girish_mn
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4/23/2008 6:09 AM
Hi, Any can help me about the below topic What is actually antipad , (according to my understanding it is athe area of copper etched away around a via or a plated through-hole on a power or ground plane , to provide voiding for other net . & this not having role in the routing layer if no shapes in that ), recently I did one design , in that there no shape in the sig layer but my customer telling that you should not route trace under the antipad ( I have not routed any trace in the plane) , please find the attched board screeshot.

remaley228
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4/23/2008 6:38 AM
The antipad is the cutout on plane layers around the through-hole pins in the above screenshot. This gap in the plane reduces the capacitance between the pins of the connector and the ground net, and improves signal integrity. We use anti-pads on all of our high speed design The pair's line impedance is determined by the width of the line used as well as distance this line sits above the ground plane. Becuase no plane is present in antipad regions, routing over antipads causes the impedance of the line to change every time the signal goes over the gap in the plane. This causes impedance discontinuities in the pair and can degrade the signal integrity of the link. In our designs, we decrease the antipad size so that the the pair is always routed over a ground plane. We also center the pair within the array of pins to keep the ground plane under the pair as consistent as possible. When this is not possible, we even sometimes place voids in the plane to make the impedance discontinuities consistent across both legs of the pair. This makes any discontinuity and the noise that it creates symmetric between both legs. Since it's symmetric, it's common-mode noise, and is rejected by the differential receiver.

Chuck Remaley Design Engineer Woodward McCoach, Inc.

andrewjw
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4/23/2008 6:48 AM
In the XL version of Allegro there is an option available to find segments that are over voids - which help you find possible impedance changes. The command for this is Display->Segments Over Voids

girish_mn
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4/23/2008 7:32 AM
Hi, thank you very much Remaley for quick fats reply, now i got the idea. but the strange thing in the allegro16.0 antipad wil not work on the plne , whatever constraint we will set that wil effect , after your reply i redused the antipad size by10mil (previously it outer dia+20mil),then i updaed the pad stack but it is not updated then I reduced the via to shpe constraint to 5mil (previously 10mil) , then updated the shape it got updated , now the trace wil run over the gnd plane it will not enter in to the void area reducing the antipad size will casue any effect ? , is there any standard minimum value for shape to via air gap . Have a pleasent day, Regards, Girish

remaley228
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4/23/2008 8:14 AM
There's no fast recommendation I can give you. We use the guidlines given by Amp for their Zd press-fit connectors. See below http://catalog.tycoelectronics.com/TE/Presentations/20GC015-1_RevB.pdf

Chuck Remaley Design Engineer Woodward McCoach, Inc.

redwire
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4/24/2008 9:39 AM
girish_mn: Why are your diff pairs coming out of the pin pairs in such an unbalanced way? Yuck. You can set Allegro up so that the pin pairs come out even. remaley228 explained the reason fairly well. Even with all this -- the diffpair signal can arrive with one leg severely out of phase with respect to the other. Anyone care to explain? :) Hint: You probably have to deal with this for 10Gbps and up signaling only...

cadpro2k
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4/24/2008 5:37 PM
Redwire, The traces route off the pads, as shown, to complete the 'length match' requirement. I've seen this any number of ways. It might look like 'yuck', but who cares? It's buried, it works, and it's matched. Whalla. :) As for the anti-pad openings, they seem excessively large to me. The problem (per your customer) could be with 'impedance control'. When these traces loose their reference to the return path (er... go over your plane opening - antipad), you could see some discontinuity (reflection?). I'd decrease the anti-pad opening, and make sure the whole traces transitions the plane. Good day. Mitch

girish_mn
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4/24/2008 9:10 PM
Thanks for valuable feedback I need to come out of pin field to match the length of pairs other wise one trce will be 25-40mils more compared to another,in this board all the pairs are having 3-5mil tolerece only , we usuaally do like this for diff pairs i dont think so it will create a problem , you have any better method of routing for diff pair Regardss, Girish Kumar INDIA

redwire
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4/25/2008 4:25 PM
Posted By cadpro2k on 4/24/2008 5:37 PM Redwire, The traces route off the pads, as shown, to complete the 'length match' requirement. I've seen this any number of ways. It might look like 'yuck', but who cares? It's buried, it works, and it's matched. Whalla. :) Mitch Ah...so thats not acceptable at the signaling speeds I work at. Two issues pop up right away. One is mode (even vs odd mode) and the other is phase. I cant introduce phase errors on my backplane (as this looks) and by attempting to correct a phase error by overcompensating here is not a good technique. Yes, it might meet the DRC rule but then the DRC rule might be wrong. :) And then theres the issue related to my pop quiz in the previous post. :) Any thoughts? Bill

rbennett
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4/25/2008 4:43 PM
The Phase shift is the most important aspect of routing differential pairs, the ideal phase shift is 0 this is what's assumed when dealing with differentials i.e. - the drivers have no scew - the signal delay between driver and receiver are equal. Adding a phase shift creates spikes at the crossing points, when a differential is out of phase by 10 / 15 degrees you need to simulate to see the signal - as the bigger the shift the bigger the common mode signal becomes. douting over voids is obvioulsy not a good idea as you are increasing the loop inductance for the return path.. You need to see what speeds your running i.e. Operating Freq (most important thing is Switching frequency) Operating Freq = 0.35 / Tr So if your fastest device on your board is 1nS then you have an Operating Freq of - 350MHz

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Forums > Silicon-package-board > PCB Design > why we should not route traces across antipad in the routing layer?.